Abstract: A system and method for dynamically modifying scheduling of scan operations for a system under test includes a processing module configured to apply input test data to the system under test based on the scan operations via a test access port and a scheduler adapted to provide the processing module with scheduling for the plurality of scan operations. The scheduler includes a circuit model of the system under test. The circuit model includes at least one attribute providing enhancing information for at least a portion of the system under test. The scheduler is adapted to schedule the scan operations based on the circuit model and to modify the schedule based on the at least one attribute. The processing module is configured to receive the modified scheduled scan operations and to apply the input test data to the system under test based on the modified scheduled scan operations.

Abstract: A distributed test architecture of transmitting boundary scan Test Access Port (TAP_signals over a serial channel is disclosed. The architecture facilitates the system testing and remote field update of distributed base stations in a wireless network. The distributed test architecture enables system testing as if the distributed units are on a backplane within the same chassis by creating a plurality of logical connections between the distributed unit and the test bus using a single bit fiber line and a five bit TAP test bus.

Abstract: The invention includes an apparatus and method for dynamically isolating a portion of a scan path of a system-on-chip. In one embodiment, an apparatus includes a scan path and control logic. The scan path includes at least a first hierarchical level, where the first hierarchical level includes a plurality of components, and a second hierarchical level having at least one component. The second hierarchical level is adapted for being selected and deselected such that the second hierarchical level is active or inactive. The control logic is adapted to filter application of at least one control signal to the at least one component of the second hierarchical level in a manner for controlling propagation of data within the second hierarchical level independent of propagation of data within the first hierarchical level.

Abstract: The invention includes an apparatuses and associated methods for controlling dynamic modification of a testing scan path using a control scan path. In one embodiment, an apparatus includes a testing scan path and a control scan path. The testing scan path includes testing components and at least one hierarchy-enabling component. In one embodiment, the control scan path includes at least one control component coupled to the at least one hierarchy-enabling component for controlling dynamic modification of the testing scan path. In one embodiment, the control scan path includes the at least one hierarchy-enabling component, wherein the at least one hierarchy-enabling component is adapted for dynamically modifying the testing scan path using the control scan path. The dynamic modification of the testing scan path may include modifying a hierarchy of the testing scan path, such as selecting or deselecting one or more hierarchical levels of the testing scan path.

Abstract: The invention includes an apparatus and method for dynamically isolating a portion of a scan path of a system-on-chip. In one embodiment, an apparatus includes a scan path and control logic. The scan path includes at least a first hierarchical level, where the first hierarchical level includes a plurality of components, and a second hierarchical level having at least one component. The second hierarchical level is adapted for being selected and deselected such that the second hierarchical level is active or inactive. The control logic is adapted to filter application of at least one control signal to the at least one component of the second hierarchical level in a manner for controlling propagation of data within the second hierarchical level independent of propagation of data within the first hierarchical level.

Abstract: The invention includes an apparatuses and associated methods for controlling dynamic modification of a testing scan path using a control scan path. In one embodiment, an apparatus includes a testing scan path and a control scan path. The testing scan path includes testing components and at least one hierarchy-enabling component. In one embodiment, the control scan path includes at least one control component coupled to the at least one hierarchy-enabling component for controlling dynamic modification of the testing scan path. In one embodiment, the control scan path includes the at least one hierarchy-enabling component, wherein the at least one hierarchy-enabling component is adapted for dynamically modifying the testing scan path using the control scan path. The dynamic modification of the testing scan path may include modifying a hierarchy of the testing scan path, such as selecting or deselecting one or more hierarchical levels of the testing scan path.

Abstract: The present invention provides a test vector manager for use with a unit under test (UUT). In one embodiment, the test vector manager includes a gateway device, coupled to the UUT, configured to provide a testing pathway for the UUT to coordinate test requests and responses for a backplane multi-drop test bus. The test vector manager also includes a test memory, coupled to the gateway device, configured to retrieve version-specific test vectors, which are resident on the UUT and correspond to the test requests. The test vector manager further includes a chain configuration logic unit, coupled to the test memory, configured to return the version-specific test vectors to the backplane multi-drop test bus employing the testing pathway. Alternatively, the test vector manager is further configured to connect the backplane multi-drop test bus to local UUT test bus and scan chain interfaces for tests using the version-specific test vectors.

Abstract: The present invention provides a system for, and method of, adaptable testing of backplane interconnections. In one embodiment, the system includes a board detector configured to determine a relative arrangement of a plurality of hardware boards populating positions associated with the backplane interconnections. Additionally, the system also includes a test coordinator coupled to the board detector and configured to adaptively backplane test at least a pair of the plurality of hardware boards based on the relative arrangement.

Abstract: A flexible Boundary Scan test system is disclosed. The system includes an interpreter module operable to execute a program element selected from a plurality of program elements that include at least one instruction type having an interface to identify and execute selected functions wherein each of the selected functions has associated therewith at least one data information item. In one aspect of the invention, selected ones of the functions are composed of a plurality of functions. In another aspect of the invention, the instruction includes parameters and adornments for determining the selected function execution.

Abstract: The positional error of a robotic manipulator (20,22) within its workspace (38) can be reduced by advantageously mapping the manipulator positional error at each of a plurality of grid points (44) within the workspace. Such mapping is carried out by placing a grid (40) containing uniformly spaced grid points (44) in the workspace and then measuring the manipulator error at each grid point. From the map of manipulator positional error values, the manipulator positional error at any point in the workspace can easily be obtained by interpolation.