Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports devices adapted for dynamically modifying the scan path of a system-on-chip (referred to herein as crossroad devices), including methods for describing such devices and use of such devices to perform testing of system-on-chips.

Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip.

Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports parallel access to one or more system-on-chip devices, including methods for describing and using parallel access for testing.

Abstract: System including backplane, and first and second circuit boards. First circuit board is attached to backplane and has first optical signal transmitter. Second circuit board is attached to backplane and has first optical signal receiver. First optical signal transmitter and first optical signal receiver are separated by free space and form optical communication link configured for circuit board test signal communication from first circuit board to second circuit board through the free space. Method includes providing backplane and first and second circuit boards, where first circuit board is attached to backplane and has first optical signal transmitter, and second circuit board is attached to backplane and has first optical signal receiver. First optical signal transmitter and first optical signal receiver are separated by free space, and form optical communication link. Method additionally includes transmitting circuit board test signal from first circuit board to second circuit board through the free space.

Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports devices adapted for dynamically modifying the scan path of a system-on-chip (referred to herein as crossroad devices), including methods for describing such devices and use of such devices to perform testing of system-on-chips.

Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip.

Abstract: System including backplane, and first and second circuit boards. First circuit board is attached to backplane and has first optical signal transmitter. Second circuit board is attached to backplane and has first optical signal receiver. First optical signal transmitter and first optical signal receiver are mutually configured and mutually aligned for circuit board test signal communication from first circuit board to second circuit board across free space. Method includes providing backplane and first and second circuit boards, where first circuit board has first optical signal transmitter and second circuit board has first optical signal receiver. Method further includes attaching first and second circuit boards to backplane, and mutually configuring and mutually aligning first optical signal transmitter and first optical signal receiver for circuit board test signal communication from first circuit board to second circuit board across free space.

Abstract: A method and system for testing circuit clusters in a boundary scan environment identifies the circuit clusters and corresponding neighboring boundary scan elements, and generates one or more test vectors to be applied to the cluster under test. The generated test vectors are serialized and input into an identified boundary scan element connected to the cluster being tested in the form of a boundary scan test chain. The output of the applied test vectors is observed from an output of another correspondingly identified boundary scan element connected to the cluster under test. During generation of test vectors a list of faults for detecting by each generated vector is maintained such that the observed output can be used to diagnose faults at the component level within the identified cluster.