Patents by Inventor Bradford L. Hunter
Bradford L. Hunter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9110488Abstract: A linear regulator and a method of regulating a supply voltage are provided. Embodiments include a linear regulator with a first feedback loop and a second feedback loop. The first feedback loop is characterized by a first bandwidth and a first gain. The first feedback loop includes a first amplifier characterized by an output impedance which is significantly reduced in order to maximize the bandwidth of the first feedback loop when driving the capacitance of a control input of a series pass element. The second feedback loop is characterized by a second bandwidth and a second gain. The second feedback loop includes a second amplifier that controls the current in the first amplifier in the first feedback loop.Type: GrantFiled: June 7, 2011Date of Patent: August 18, 2015Assignee: International Business Machines CorporationInventors: Bradford L. Hunter, Todd M. Rasmus
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Patent number: 8456935Abstract: In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.Type: GrantFiled: November 16, 2011Date of Patent: June 4, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Bradford L. Hunter, Shayan Zhang
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Publication number: 20120313597Abstract: A linear regulator and a method of regulating a supply voltage are provided. Embodiments include a linear regulator with a first feedback loop and a second feedback loop. The first feedback loop is characterized by a first bandwidth and a first gain. The first feedback loop includes a first amplifier characterized by an output impedance which is significantly reduced in order to maximize the bandwidth of the first feedback loop when driving the capacitance of a control input of a series pass element. The second feedback loop is characterized by a second bandwidth and a second gain. The second feedback loop includes a second amplifier that controls the current in the first amplifier in the first feedback loop.Type: ApplicationFiled: June 7, 2011Publication date: December 13, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bradford L. Hunter, Todd M. Rasmus
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Patent number: 8230382Abstract: A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters.Type: GrantFiled: January 28, 2010Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Robert J. Gauthier, Jr., Bradford L. Hunter, Amol A. Joshi, Junjun Li, Gregory Joseph Schroer
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Publication number: 20120063249Abstract: In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.Type: ApplicationFiled: November 16, 2011Publication date: March 15, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Bradford L. Hunter, Shayan Zhang
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Patent number: 8077533Abstract: In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.Type: GrantFiled: January 23, 2006Date of Patent: December 13, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Bradford L. Hunter, Shayan Zhang
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Publication number: 20110185332Abstract: A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters.Type: ApplicationFiled: January 28, 2010Publication date: July 28, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert J. Gauthier, JR., Bradford L. Hunter, Amol A. Joshi, Junjun Li, Gregory Joseph Schroer
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Patent number: 7932641Abstract: A method and structure for preventing operation of a circuit in a high current operating region by disabling a start-up circuit until a power supply headroom is detected at a predetermined voltage level.Type: GrantFiled: June 11, 2007Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Bradford L. Hunter, Joseph A. Iadanza
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Patent number: 7793172Abstract: Methods and systems for configuring characteristics associated with at least one portion of a memory array comprising addressable units are provided. In one aspect, a method for controlling a power supply voltage for a memory array comprises detecting whether an error occurred in performing a read operation on an addressable unit of the memory array using a first power supply voltage coupled to the memory array. The method further comprises incrementing an error counter for tracking an error count associated with the memory array and switching the memory array to a second power supply voltage if the error count is equal to or exceeds an error threshold for the memory array. The method further comprises, based on at least one condition, switching the memory array to the first power supply voltage and resetting the error counter to an initial value.Type: GrantFiled: September 28, 2006Date of Patent: September 7, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Klas M. Bruce, Andrew C. Russell, Shayan Zhang, Bradford L. Hunter
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Patent number: 7684264Abstract: A memory system including a random access memory (RAM) array and a corresponding redundant RAM array which stores information redundant to the RAM array, where a designed cell circuit topology of cells within the redundant RAM array differs from a designed cell circuit topology of cells within the RAM array. The redundant RAM array is selectively accessed when accessing the RAM array to store data to the redundant RAM array for failed cells of the RAM array.Type: GrantFiled: January 26, 2007Date of Patent: March 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Bradford L. Hunter, James D. Burnett, Andrew C. Russell, Shayan Zhang
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Patent number: 7598784Abstract: In accordance with the present disclosure, an electronic circuit of an integrated circuit is configured to receive an input signal that has a falling transition and a rising transition and provide a selectable delay of the input signal transitions on its output. The output of the disclosed circuit can provide a falling transition delayed in response to a falling edge control signal control, and a rising transition delayed in response to a rising edge control signal. The disclosed circuit can have a rising transition control circuit (RTCC), a falling transition control circuit (FTCC) and an output circuit.Type: GrantFiled: October 7, 2005Date of Patent: October 6, 2009Assignee: Freescale Semiconductor, Inc.Inventor: Bradford L. Hunter
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Patent number: 7564307Abstract: A structure and related design structure for providing a common mode feedback to a differential amplifier are disclosed. A common mode feedback amplifier is connected to a differential amplifier to provide common mode feedback voltage thereto. An input of the common mode feedback amplifier is shorted to an output terminal of the differential amplifier during a sampling phase, and is coupled to the differential output voltage through two matched capacitors during a holding phase.Type: GrantFiled: September 4, 2007Date of Patent: July 21, 2009Assignee: International Business Machines CorporationInventors: Bradford L. Hunter, Gregory J. Schroer
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Patent number: 7523373Abstract: A method includes an integrated circuit with a memory. The memory operates with an operating voltage. A value of a minimum operating voltage of the memory is determined. The value of the minimum operating voltage is stored in a non-volatile memory location that maybe a non-volatile register. This minimum operating voltage information can then be used in determining when an alternative power supply voltage may be switched to the memory or ensuring that the minimum voltage is otherwise met. The minimum voltage can be used only internal to the integrated circuit or also provided externally to a user.Type: GrantFiled: August 30, 2006Date of Patent: April 21, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Andrew C. Russell, David R. Bearden, Bradford L. Hunter, Shayan Zhang
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Publication number: 20090058526Abstract: A structure and related design structure for providing a common mode feedback to a differential amplifier are disclosed. A common mode feedback amplifier is connected to a differential amplifier to provide common mode feedback voltage thereto. An input of the common mode feedback amplifier is shorted to an output terminal of the differential amplifier during a sampling phase, and is coupled to the differential output voltage through two matched capacitors during a holding phase.Type: ApplicationFiled: September 4, 2007Publication date: March 5, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bradford L. Hunter, Gregory J. Schroer
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Publication number: 20090058473Abstract: An approach that provides active pre-emphasis for a passive RC network is described. In one embodiment, there is a circuit that comprises an RC filter including a resistive divider formed from a first resistor and a second resistor and a filtering capacitor. The first resistor is configured to receive an input voltage and the second resistor and filtering capacitor are in parallel and configured to generate a reference voltage that is a percentage of the input voltage. An operational amplifier is coupled to the RC filter. A first multiplexer controlled by a pulse pre-emphasis signal is coupled to the operational amplifier and the RC filter. A second multiplexer controlled by a sample and hold clocking signal has inputs that are coupled to the first multiplexer and ground.Type: ApplicationFiled: September 5, 2007Publication date: March 5, 2009Applicant: International Business Machines CorporationInventor: Bradford L. Hunter
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Publication number: 20080304192Abstract: A method and structure for preventing operation of a circuit in a high current operating region by disabling a start-up circuit until a power supply headroom is detected at a predetermined voltage level.Type: ApplicationFiled: June 11, 2007Publication date: December 11, 2008Inventors: Bradford L. Hunter, Joseph A. Iadanza
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Publication number: 20080181034Abstract: A memory system including a random access memory (RAM) array and a corresponding redundant RAM array which stores information redundant to the RAM array, where a designed cell circuit topology of cells within the redundant RAM array differs from a designed cell circuit topology of cells within the RAM array. The redundant RAM array is selectively accessed when accessing the RAM array to store data to the redundant RAM array for failed cells of the RAM array.Type: ApplicationFiled: January 26, 2007Publication date: July 31, 2008Inventors: Bradford L. Hunter, James D. Burnett, Andrew C. Russell, Shayan Zhang
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Publication number: 20080091990Abstract: Methods and systems for configuring characteristics associated with at least one portion of a memory array comprising addressable units are provided. In one aspect, a method for controlling a power supply voltage for a memory array comprises detecting whether an error occurred in performing a read operation on an addressable unit of the memory array using a first power supply voltage coupled to the memory array. The method further comprises incrementing an error counter for tracking an error count associated with the memory array and switching the memory array to a second power supply voltage if the error count is equal to or exceeds an error threshold for the memory array. The method further comprises, based on at least one condition, switching the memory array to the first power supply voltage and resetting the error counter to an initial value.Type: ApplicationFiled: September 28, 2006Publication date: April 17, 2008Inventors: Klas M. Bruce, Andrew C. Russell, Shayan Zhang, Bradford L. Hunter
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Publication number: 20080082873Abstract: A method includes an integrated circuit with a memory. The memory operates with an operating voltage. A value of a minimum operating voltage of the memory is determined. The value of the minimum operating voltage is stored in a non-volatile memory location that maybe a non-volatile register. This minimum operating voltage information can then be used in determining when an alternative power supply voltage may be switched to the memory or ensuring that the minimum voltage is otherwise met. The minimum voltage can be used only internal to the integrated circuit or also provided externally to a user.Type: ApplicationFiled: August 30, 2006Publication date: April 3, 2008Inventors: Andrew C. Russell, David R. Bearden, Bradford L. Hunter, Shayan Zhang
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Patent number: 7336533Abstract: An electronic device includes a memory cell that utilizes a bi-directional low impedance, low voltage drop full pass gate to connect a bit cell to a bit write line during a write phase, and during a read phase the full pass gate can remain off and a high input impedance read port can acquire and transmit the logic state stored by the memory cell to another subsystem. The full pass gate can be implemented by connecting a P type metal semiconductor field effect transistor (PMOS) in parallel with an NMOS device and driving the gates of the transistors with a differential signal. When a write operation requires a current to flow in a first direction, the PMOS device provides a negligible voltage drop, and when the write operation requires current to flow in a second or the opposite direction, the NMOS device can provide a negligible voltage.Type: GrantFiled: January 23, 2006Date of Patent: February 26, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Bradford L. Hunter, James D. Burnett, Jack M. Higman