Abstract: In a communications system (10), data is transferred from a physical interface section (64) and two processors, a receive processor (66) and a transmit processor (68). The data is transferred from the physical interface (64) to the receive processor (66) through a receive fifo (112). Data is transferred from the transmit processor (68) to the physical interface (64) through a transmit fifo (110). To prevent the transmit processor (68) and the receive processor (66) from processing data faster than the physical interface (64), clock disabling circuits (1030 and 1032) are utilized wherein the system clock (1033) to the receive processor (66) will be disabled when both the receive fifo (112) is empty and the current instruction performs a read from the receive fifo (112). The system clock (1050) to the transmit processor (68) will be disabled when both the transmit fifo (110) is full and the current instruction executes a write to the transmit fifo.