Abstract: A system and method for dynamically modifying scheduling of scan operations for a system under test includes a processing module configured to apply input test data to the system under test based on the scan operations via a test access port and a scheduler adapted to provide the processing module with scheduling for the plurality of scan operations. The scheduler includes a circuit model of the system under test. The circuit model includes at least one attribute providing enhancing information for at least a portion of the system under test. The scheduler is adapted to schedule the scan operations based on the circuit model and to modify the schedule based on the at least one attribute. The processing module is configured to receive the modified scheduled scan operations and to apply the input test data to the system under test based on the modified scheduled scan operations.

Abstract: A position-based scheduling capability supports interaction between one or more user applications and a scheduler for performing testing via a scan chain of a unit under test. The scheduler receives access requests from one or more user applications, where each access request is a request for access to a segment of the scan chain, respectively. The scheduler determines scheduling of the access requests using a circuit model configured to represent an ordering of the segments of the scan chain. The scheduler may provide the access responses to the user application(s) from which the access requests are received, thereby enabling the user application(s) to issue test operations toward a processor configured to generate test data to be applied to the scan chain. The scheduler may obtain the test operations and send the test operations toward a processor configured to generate test data to be applied to the scan chain.

Abstract: A deferred scheduling capability supports deferred scheduling when performing testing via a scan chain of a unit under test. A processing module is configured to receive a plurality of test operations associated with a plurality of segments of a unit under test and to generate therefrom input test data configured to be applied to the unit under test via a Test Access Port (TAP). A reordering buffer module is configured to receive the input test data from the processing element and to buffer the input test data in a manner for reordering the input test data to compose an input test vector for a scan chain of the unit under test. A vector transformation module is configured to receive the input test vector from the reordering buffer module and to apply a vector transformation for the input test vector.

Abstract: An apparatus is provided for performing testing of at least a portion of a system under test via a Test Access Port (TAP) configured to access the system under test. The apparatus includes a first processor for executing instructions adapted for controlling testing of at least a portion of the system under test via the TAP, and a second processor for supporting an interface to the TAP. The first processor is configured for detecting, during execution of the test instructions, TAP-related instructions associated with control of the TAP, and propagating the TAP-related instructions toward the second processor. The second processor is configured for receiving the TAP-related instructions detected by the first processor and processing the TAP-related instructions. The first processor is configured for performing at least one task contemporaneously with processing of the TAP-related instructions by the second processor. An associated method also is provided.

Abstract: A virtual In-Circuit Emulation (ICE) capability is provided herein for supporting testing of Joint Test Action Group (JTAG) hardware. A Virtual ICE Driver is configured for enabling any debug software to interface with target hardware in a flexible and scalable manner. The Virtual ICE Driver is configured such that the test instruction set used with the Virtual ICE Driver is not required to compute vectors, as the JTAG operations are expressed as local native instructions on scan segments, thereby enabling ICE resources to be accessed directly. The Virtual ICE Driver is configured such that ICE may be combined with instrument-based JTAG approaches (e.g., the IEEE P1687 standard and other suitable approaches).

Abstract: An apparatus for use in testing at least a portion of a system under test via a Test Access Port (TAP) is provided. The apparatus includes a memory for storing a set of instructions of a test instruction set architecture and a processor executing the set of instructions of the test instruction set architecture for testing at least a portion of the system under test via the TAP. The set of instructions of the test instruction set architecture includes a first set of instructions including a plurality of instructions of an Instruction Set Architecture (ISA) supported by the processor and a second set of instructions including a plurality of test instructions associated with the TAP. The instructions of the first set of instructions and the instructions of the second set of instructions are integrated to form the set of instructions of the test instruction set architecture.

Abstract: A scan chain security capability is provided herein. The scan chain security capability enables secure control over normal use of a scan chain of a system, e.g., for purposes such as testing prior to deployment or sale of the system, in-field testing after deployment or sale of the system, in-field modification of the system, and the like. The scan chain security capability enables secure control over normal use of a scan chain by enabling control over interruption of a scan chain and re-establishment of an interrupted scan chain. A scan chain security component is configured for removing an open-circuit condition from the scan chain in response to a control signal. The control signal may be generated in response to validation of a security key, in response to successful completion of a challenge-based authentication process, or in response to any other suitable validation or authentication.

Abstract: A position-based scheduling capability supports interaction between one or more user applications and a scheduler for performing testing via a scan chain of a unit under test. The scheduler receives access requests from one or more user applications, where each access request is a request for access to a segment of the scan chain, respectively. The scheduler determines scheduling of the access requests using a circuit model configured to represent an ordering of the segments of the scan chain. The scheduler may provide the access responses to the user application(s) from which the access requests are received, thereby enabling the user application(s) to issue test operations toward a processor configured to generate test data to be applied to the scan chain. The scheduler may obtain the test operations and send the test operations toward a processor configured to generate test data to be applied to the scan chain.

Abstract: A deferred scheduling capability supports deferred scheduling when performing testing via a scan chain of a unit under test. A processing module is configured to receive a plurality of test operations associated with a plurality of segments of a unit under test and to generate therefrom input test data configured to be applied to the unit under test via a Test Access Port (TAP). A reordering buffer module is configured to receive the input test data from the processing element and to buffer the input test data in a manner for reordering the input test data to compose an input test vector for a scan chain of the unit under test. A vector transformation module is configured to receive the input test vector from the reordering buffer module and to apply a vector transformation for the input test vector.

Abstract: A scan chain security capability is provided herein. The scan chain security capability enables secure control over normal use of a scan chain of a system, e.g., for purposes such as testing prior to deployment or sale of the system, in-field testing after deployment or sale of the system, in-field modification of the system, and the like. The scan chain security capability enables secure control over normal use of a scan chain by enabling control over interruption of a scan chain and re-establishment of an interrupted scan chain. A scan chain security component is configured for removing an open-circuit condition from the scan chain in response to a control signal. The control signal may be generated in response to validation of a security key, in response to successful completion of a challenge-based authentication process, or in response to any other suitable validation or authentication.

Abstract: A virtual In-Circuit Emulation (ICE) capability is provided herein for supporting testing of Joint Test Action Group (JTAG) hardware. A Virtual ICE Driver is configured for enabling any debug software to interface with target hardware in a flexible and scalable manner. The Virtual ICE Driver is configured such that the test instruction set used with the Virtual ICE Driver is not required to compute vectors, as the JTAG operations are expressed as local native instructions on scan segments, thereby enabling ICE resources to be accessed directly. The Virtual ICE Driver is configured such that ICE may be combined with instrument-based JTAG approaches (e.g., the IEEE P1687 standard and other suitable approaches).

Abstract: An apparatus for use in testing at least a portion of a system under test via a Test Access Port (TAP) is provided. The apparatus includes a memory for storing a set of instructions of a test instruction set architecture and a processor executing the set of instructions of the test instruction set architecture for testing at least a portion of the system under test via the TAP. The set of instructions of the test instruction set architecture includes a first set of instructions including a plurality of instructions of an Instruction Set Architecture (ISA) supported by the processor and a second set of instructions including a plurality of test instructions associated with the TAP. The instructions of the first set of instructions and the instructions of the second set of instructions are integrated to form the set of instructions of the test instruction set architecture.

Abstract: An apparatus is provided for performing testing of at least a portion of a system under test via a Test Access Port (TAP) configured to access the system under test. The apparatus includes a first processor for executing instructions adapted for controlling testing of at least a portion of the system under test via the TAP, and a second processor for supporting an interface to the TAP. The first processor is configured for detecting, during execution of the test instructions, TAP-related instructions associated with control of the TAP, and propagating the TAP-related instructions toward the second processor. The second processor is configured for receiving the TAP-related instructions detected by the first processor and processing the TAP-related instructions. The first processor is configured for performing at least one task contemporaneously with processing of the TAP-related instructions by the second processor. An associated method also is provided.

Abstract: A method is provided for testing a portion of a system under test via a scan chain of the system under test. The method includes decomposing the scan chain into a plurality of segments, generating a set of instructions for testing the portion of the system under test, and executing the set of instructions for testing the portion of the system under test. The scan chain is composed of a plurality of elements, and each segment includes at least one of the elements of the scan chain. The set of instructions includes a plurality of processor instructions associated with an Instruction Set Architecture (ISA), and a plurality of test instructions. The test instructions include, for each of the plurality of segments of the scan chain, at least one scan operation to be performed on the segment. An associated apparatus also is provided.

Abstract: The present invention provides a test vector manager for use with a unit under test (UUT). In one embodiment, the test vector manager includes a gateway device, coupled to the UUT, configured to provide a testing pathway for the UUT to coordinate test requests and responses for a backplane multi-drop test bus. The test vector manager also includes a test memory, coupled to the gateway device, configured to retrieve version-specific test vectors, which are resident on the UUT and correspond to the test requests. The test vector manager further includes a chain configuration logic unit, coupled to the test memory, configured to return the version-specific test vectors to the backplane multi-drop test bus employing the testing pathway. Alternatively, the test vector manager is further configured to connect the backplane multi-drop test bus to local UUT test bus and scan chain interfaces for tests using the version-specific test vectors.

Abstract: The present invention provides a system for, and method of, adaptable testing of backplane interconnections. In one embodiment, the system includes a board detector configured to determine a relative arrangement of a plurality of hardware boards populating positions associated with the backplane interconnections. Additionally, the system also includes a test coordinator coupled to the board detector and configured to adaptively backplane test at least a pair of the plurality of hardware boards based on the relative arrangement.

Abstract: A system for, and method of, emulating hardware failures and a Joint Test Action Group (JTAG) test tool incorporating the same. In one embodiment, the system includes: (1) a vector generator configured to generate at least one device failure emulation vector and (2) a JTAG interface associable with the vector generator and configured to deliver the device failure emulation vector to hardware thereby to test system software associated with the hardware.

Abstract: A distributed test architecture of transmitting boundary scan Test Access Port (TAP_signals over a serial channel is disclosed. The architecture facilitates the system testing and remote field update of distributed base stations in a wireless network. The distributed test architecture enables system testing as if the distributed units are on a backplane within the same chassis by creating a plurality of logical connections between the distributed unit and the test bus using a single bit fiber line and a five bit TAP test bus.

Abstract: A flexible Boundary Scan test system is disclosed. The system includes an interpreter module operable to execute a program element selected from a plurality of program elements that include at least one instruction type having an interface to identify and execute selected functions wherein each of the selected functions has associated therewith at least one data information item. In one aspect of the invention, selected ones of the functions are composed of a plurality of functions. In another aspect of the invention, the instruction includes parameters and adornments for determining the selected function execution.