Patents by Inventor Bradley Burres
Bradley Burres has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11941458Abstract: Examples described herein relate to migrating a virtualized execution environment from a first platform to a second platform while retaining use of namespace identifiers and permitting issuance of storage transactions by the virtualized execution environment. The first platform can include a first central processing unit or a first network interface. The second platform can include a central processing unit that is different that the first central processing unit and a network interface that is the same or different than the first network interface. The second platform can retain access permissions and target media format independent of one or more identifiers associated with the migrated virtualized execution environment at the second platform. Unperformed storage transactions can be migrated to the second platform for execution.Type: GrantFiled: March 10, 2020Date of Patent: March 26, 2024Assignee: SK Hynix NAND Product Solutions Corp.Inventors: Jose Niell, Bradley A. Burres, Kiel Boyle, David Noeldner, Keith Shaw, Karl P. Brummel
-
Publication number: 20240012769Abstract: Examples described herein relate to a network interface device. In some examples, the network interface device includes a network interface, a direct memory access (DMA) circuitry, a host interface, memory, one or more processors, and circuitry to: based on a configuration of operation specifying a standalone operation, cause the network interface device to operate in standalone to execute one or more applications and based on a configuration of operation specifying a companion operation, cause the network interface device to operate in companion to provide at least one host system with access to one or more hardware resources accessible by the network interface device.Type: ApplicationFiled: September 20, 2023Publication date: January 11, 2024Inventors: Francesc GUIM BERNAT, Manish DAVE, Vered BAR BRACHA, Bradley A. BURRES, Uzair QURESHI, Joseph GRECCO, Paul KAPPLER, Dirk F. BLEVINS, Mukesh Gangadhar BHAVANI VENKATESAN, Hariharan M, Marek PIOTROWSKI, Dhanya PILLAI, John MANGAN, Mandar CHINCHOLKAR, Eoin WALSH, Sumit MOHAN, Ned SMITH, Tushar Sudhakar GOHAD
-
Publication number: 20230367729Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.Type: ApplicationFiled: May 18, 2023Publication date: November 16, 2023Inventors: Balaji PARTHASARATHY, Ramamurthy KRITHIVAS, Bradley BURRES, Pawel SZYMANSKI, Yi-Feng LIU
-
Publication number: 20230333921Abstract: Examples described herein relate to a host interface and circuitry. In some examples, the circuitry, when coupled to a physical device, is to: perform operations of a hypervisor. In some examples, the host interface is configured to route first communications to the circuitry instead of the physical device and route second communications to the physical device. In some examples, the physical device is accessible as a virtual device via the host interface.Type: ApplicationFiled: February 21, 2023Publication date: October 19, 2023Inventors: Noam ELATI, Piotr UMINSKI, Boris KLEIMAN, Lloyd DCRUZ, Bradley A. BURRES, Salma Mirza JOHNSON, Thomas E. WILLIS, Duane E. GALBI
-
Patent number: 11693807Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.Type: GrantFiled: March 19, 2021Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Balaji Parthasarathy, Ramamurthy Krithivas, Bradley A. Burres, Pawel Szymanski, Yi-Feng Liu
-
Publication number: 20230185747Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller’s performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: ApplicationFiled: February 8, 2023Publication date: June 15, 2023Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
-
Publication number: 20230153143Abstract: Creating hybrid virtual devices using a plurality of physical functions. A processor of a device may identify a plurality of physical functions accessible to the device, the plurality of physical functions including a first physical function and a second physical function. The processor may create a virtual device to comprise the first physical function to provide a first capability and the second physical function to provide a second capability, wherein the first capability and second capability are different capabilities.Type: ApplicationFiled: January 17, 2023Publication date: May 18, 2023Applicant: Intel CorporationInventors: SHAOPENG HE, ANJALI SINGHAI JAIN, UTKARSH Y. KAKAIYA, YADONG LI, ELIEL LOUZOUN, KUN TIAN, BRADLEY BURRES, RORY HARRIS, YAN ZHAO
-
Publication number: 20230139762Abstract: Examples described herein relate to a network interface device that includes a programmable event processing architecture comprising a plurality of programmable event processors. When the plurality of programmable event processors are operational, one or more of the programmable event processors are to perform memory accesses separate from compute operations, group one or more events into at least one group, enforce atomic processing of other events within a group of the at least one group, wherein the atomic processing comprises propagation of state changes to among events of the group, and perform parallel processing of events belonging to different groups.Type: ApplicationFiled: December 27, 2022Publication date: May 4, 2023Inventors: Stephen IBANEZ, Robert SOUTHWORTH, Salma Mirza JOHNSON, Vered BAR BRACHA, Bradley A. BURRES
-
Publication number: 20230127722Abstract: Examples described herein relate to a network interface device that includes a programmable event processing architecture that includes a plurality of programmable event processors. In some examples, the plurality of programmable event processors are to perform memory accesses separate from compute operations. In some examples, the plurality of programmable event processors are to group one or more events into at least one group. In some examples, the plurality of programmable event processors are to perform parallel processing of events belonging to different groups. In some examples, the plurality of programmable event processors are programmed to perform at least one transport protocol.Type: ApplicationFiled: December 27, 2022Publication date: April 27, 2023Inventors: Stephen IBANEZ, Robert SOUTHWORTH, Salma Mirza JOHNSON, Vered BAR BRACHA, Bradley A. BURRES
-
Publication number: 20230108461Abstract: Examples described herein relate to circuitry configured to generate at least one virtual device interface to utilize the processor circuitry and provide the at least one virtual device interface to a server to assign to a process to provide the process with capability to utilize the processor circuitry. In some examples, the processor circuitry is to perform one or more of local area network access, cryptographic processing, and/or storage access. In some examples, the storage access comprises access to one or more Non-volatile Memory Express (NVMe) devices.Type: ApplicationFiled: November 30, 2022Publication date: April 6, 2023Inventors: Shaopeng HE, Anjali Singhai JAIN, Yadong LI, Eliel LOUZOUN, Bradley A. BURRES, Utkarsh Y. KAKAIYA, Kun TIAN, Baolu LU, Yan ZHAO, Madhusudan CHITTIM MUNIRATHNAM, Lingyu LIU
-
Publication number: 20230096451Abstract: Techniques for remote disaggregated infrastructure processing units (IPUs) are described. An apparatus described herein includes an interconnect controller to receive a transaction layer packet (TLP) from a host compute node; identify a sender and a destination from the TLP; and provide, to a content addressable memory (CAM), a key determined from the sender and the destination. The apparatus as described herein can further include core circuitry communicably coupled to the interconnect controller, the core circuitry to determine an output of the CAM based on the key, the output comprising a network address of an infrastructure processing unit (IPU) assigned to the host compute node, wherein the IPU is disaggregated from the host compute node over a network; and send the TLP to the IPU using a transport protocol.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Salma Johnson, Duane Galbi, Bradley Burres, Jose Niell, Jeongnim Kim, Reshma Lal, Anandhi Jayakumar, Mrittika Ganguli, Thomas Willis
-
Patent number: 11604746Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: GrantFiled: July 22, 2020Date of Patent: March 14, 2023Assignee: SK hynix NAND Product Solutions Corp.Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
-
Patent number: 11449446Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: GrantFiled: July 22, 2020Date of Patent: September 20, 2022Assignee: Intel CorporationInventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
-
Publication number: 20220224746Abstract: Examples described herein relate to a network interface device that includes circuitry to: receive a request to perform offloaded media encoding and packetization prior to transmission of the media to a receiver, wherein the media comprises video and audio; perform encoding of the media; perform packetization of the encoded media into one or more packets based on Real-time Transport Protocol (RTP) protocol; and cause transmission of the one or more packets to the receiver.Type: ApplicationFiled: April 1, 2022Publication date: July 14, 2022Inventors: Yadong LI, Changliang L. WANG, Bradley A. BURRES
-
Publication number: 20220114030Abstract: Examples described herein relate to a network interface device that includes circuitry to perform operations, offloaded from a host, to identify at least one locator of at least one target storage associated with a storage access command based on operations selected from among multiple available operations, wherein the available operations comprise two or more: entry lookup by the network interface device, hash-based calculation on the network interface device, or control plane processing on the network interface device.Type: ApplicationFiled: December 23, 2021Publication date: April 14, 2022Inventors: Salma Mirza JOHNSON, Jose NIELL, Bradley A. BURRES, Yadong LI, Scott D. PETERSON, Tony HURSON, Sujoy SEN
-
Publication number: 20210326285Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.Type: ApplicationFiled: March 19, 2021Publication date: October 21, 2021Inventors: Balaji PARTHASARATHY, Ramamurthy KRITHIVAS, Bradley A. BURRES, Pawel SZYMANSKI, Yi-Feng LIU
-
Publication number: 20210150074Abstract: Methods and apparatus for Virtual Machine (VM) encryption of block storage with end-to-end data integrity protection in a SmartNIC. For a Write operation, the NIC is configured to encrypt a data block, append the encrypted data block with protection information (PI) generated using data in the data block to generate a protected data block and forward the protected data block onto a network or fabric to be delivered to a storage node. For a Read operation, the NIC is configured to receive a protected data block comprising cipher text including encrypted payload data concatenated with an encrypted inner PI and an outer PI, use the inner and outer PIs to perform PI checks, decrypt the cipher text to extract payload data, and forward or write at least the payload to a host. The inner and outer PIs and data formats are compliant with an NVMe specification.Type: ApplicationFiled: December 23, 2020Publication date: May 20, 2021Inventors: Jose Niell, Kiel Boyle, Bradley Burres
-
Patent number: 10956351Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.Type: GrantFiled: September 10, 2019Date of Patent: March 23, 2021Assignee: Intel CorporationInventors: Balaji Parthasarathy, Ramamurthy Krithivas, Bradley Burres, Pawel Szymanski, Yi-Feng Liu
-
Patent number: 10929323Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.Type: GrantFiled: October 14, 2019Date of Patent: February 23, 2021Assignee: Intel CorporationInventors: Ren Wang, Yipeng Wang, Andrew Herdrich, Jr-Shian Tsai, Tsung-Yuan C. Tai, Niall D. McDonnell, Hugh Wilkinson, Bradley A. Burres, Bruce Richardson, Namakkal N. Venkatesan, Debra Bernstein, Edwin Verplanke, Stephen R. Van Doren, An Yan, Andrew Cunningham, David Sonnier, Gage Eads, James T. Clee, Jamison D. Whitesell, Jerry Pirog, Jonathan Kenny, Joseph R. Hasting, Narender Vangati, Stephen Miller, Te K. Ma, William Burroughs
-
Patent number: 10884968Abstract: Technologies for flexible I/O protocol acceleration include a computing device having a root complex, a smart endpoint coupled to the root complex, and an offload complex coupled to the smart endpoint. The smart endpoint receives an I/O transaction that originates from the root complex and parses the I/O transaction based on an I/O protocol and identifies an I/O command. The smart endpoint may parse the I/O transaction based on endpoint firmware that may be programmed by the computing device. The smart endpoint accelerates the I/O command and provides a smart context to the offload complex. The smart endpoint may copy the I/O command to memory of the smart endpoint or the offload complex. The smart endpoint may identify protocol data based on the I/O command and copy the protocol data to the memory of the smart endpoint or the offload complex. Other embodiments are described and claimed.Type: GrantFiled: March 27, 2019Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Matthew J. Adiletta, Bradley Burres, Duane Galbi, Amit Kumar, Yadong Li, Salma Mirza, Jose Niell, Thomas E. Willis, William Duggan