Patents by Inventor Bradley C. Kuszmaul
Bradley C. Kuszmaul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150370860Abstract: A method, apparatus and computer program product for storing data in a disk storage system is presented. A high-performance dictionary data structure is defined. The dictionary data structure is stored on a disk storage system. Key-value pairs can be inserted and deleted into the dictionary data structure. Updates run faster than one insertion per disk-head movement. The structure can also be stored on any system with two or more levels of memory. The dictionary is high performance and supports with full transactional semantics, concurrent access from multiple transactions, and logging and recovery. Keys can be looked up with only a logarithmic number of transfers, even for keys that have been recently inserted or deleted. Queries can be performed on ranges of key-value pairs, including recently inserted or deleted pairs, at a constant fraction of the bandwidth of the disk.Type: ApplicationFiled: February 24, 2015Publication date: December 24, 2015Applicant: Percona, LLCInventors: Michael A. Bender, Martin Farach-Colton, Yonatan R. Fogel, Zardosht Kasheff, Bradley C. Kuszmaul, Vincenzo Liberatore, Barry Perlman, Rich Prohaska, David S. Wells
-
Publication number: 20150355977Abstract: A system and method for backing up data on computer-readable physical medium, especially useful for databases, such as those using POSIX standard function calls, whereby select operations performed by a user of the database are intercepted and, while performed, are also translated into a shadow file having information about a database file to be backed up and the operations performed on that file. The resulting shadow file can be used to reconstitute the database file. In another mode of operation, the system and method create a copy of the database and concurrently make the same changes to the copy as the user commands while also concurrently keeping a shadow file system related to the database copy.Type: ApplicationFiled: June 10, 2014Publication date: December 10, 2015Inventors: Bradley C. Kuszmaul, Christian E. Rober
-
Publication number: 20150347477Abstract: An indexing system and method for a filesystem, such as a database using the POSIX application programming interface, uses two fractal tree indices, a metadata index mapping the full pathname of files to file metadata, preferably data such as returned with a struct stat call, and a data index mapping pathname and block number to a datablock of a predetermined size, optionally a fixed size. The data index has keys ordered lexicographically, and the system and method allows for modifying existing keys, and creating new keys if there is no existing key, for writes smaller than the predetermined block size and for unaligned writes. The invention provides at least about an order of magnitude improvement in microdata operations (such as creating and scanning files smaller than a predetermined size, such as 512-byte files), and has write times comparable with existing file systems.Type: ApplicationFiled: May 30, 2014Publication date: December 3, 2015Inventors: John Esmet, Michael A. Bender, Martin L. Farach-Colton, Bradley C. Kuszmaul
-
Patent number: 8996563Abstract: A method, apparatus and computer program product for storing data in a disk storage system is presented. A high-performance dictionary data structure is defined. The dictionary data structure is stored on a disk storage system. Key-value pairs can be inserted and deleted into the dictionary data structure. Updates run faster than one insertion per disk-head movement. The structure can also be stored on any system with two or more levels of memory. The dictionary is high performance and supports with full transactional semantics, concurrent access from multiple transactions, and logging and recovery. Keys can be looked up with only a logarithmic number of transfers, even for keys that have been recently inserted or deleted. Queries can be performed on ranges of key-value pairs, including recently inserted or deleted pairs, at a constant fraction of the bandwidth of the disk.Type: GrantFiled: April 6, 2010Date of Patent: March 31, 2015Assignee: Tokutek, Inc.Inventors: Michael A. Bender, Martin Farach-Colton, Yonatan R. Fogel, Zardosht Kasheff, Bradley C. Kuszmaul, Vincenzo Liberatore, Barry Perlman, Rich Prohaska, David S. Wells
-
Patent number: 8489638Abstract: A method, apparatus and computer program product for storing data in a disk storage system is presented. A dictionary data structure is defined and stored on the disk storage system. Key-value pairs can be inserted and deleted into the dictionary data structure, with full transactional semantics, at a rate that is faster than one insertion per disk-head movement. Keys can be looked up with only a logarithmic number of transfers, even for keys that have been recently inserted or deleted. Queries can be performed on ranges of key-value pairs, including recently inserted or deleted pairs, at a constant fraction of the bandwidth of the disk. The dictionary employs indirect logging for physical block logging.Type: GrantFiled: May 21, 2012Date of Patent: July 16, 2013Assignees: Massachusetts Institute of Technology, Research Foundation of State University of New YorkInventors: Bradley C. Kuszmaul, Michael A. Bender, Martin Farach-Colton
-
Publication number: 20130080709Abstract: A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line are not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.Type: ApplicationFiled: November 21, 2012Publication date: March 28, 2013Inventors: Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson, Bradley C. Kuszmaul, Krste Asanovic
-
Patent number: 8321634Abstract: A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.Type: GrantFiled: April 11, 2011Date of Patent: November 27, 2012Assignee: Silicon Graphics International Corp.Inventors: Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson, Bradley C. Kuszmaul, Krste Asanovic
-
Publication number: 20120254253Abstract: A method, apparatus and computer program product for storing data in a disk storage system is presented. A dictionary data structure is defined and stored on the disk storage system. Key-value pairs can be inserted and deleted into the dictionary data structure, with full transactional semantics, at a rate that is faster than one insertion per disk-head movement. Keys can be looked up with only a logarithmic number of transfers, even for keys that have been recently inserted or deleted. Queries can be performed on ranges of key-value pairs, including recently inserted or deleted pairs, at a constant fraction of the bandwidth of the disk. The dictionary employs indirect logging for physical block logging.Type: ApplicationFiled: May 21, 2012Publication date: October 4, 2012Inventors: Bradley C. Kuszmaul, Michael A. Bender, Martin Farach-Colton
-
Patent number: 8185551Abstract: A method, apparatus and computer program product for storing data in a disk storage system is presented. A dictionary data structure is defined and stored on the disk storage system. Key-value pairs can be inserted and deleted into the dictionary data structure, with full transactional semantics, at a rate that is faster than one insertion per disk-head movement. Keys can be looked up with only a logarithmic number of transfers, even for keys that have been recently inserted or deleted. Queries can be performed on ranges of key-value pairs, including recently inserted or deleted pairs, at a constant fraction of the bandwidth of the disk. The dictionary employs indirect logging for physical block logging.Type: GrantFiled: June 8, 2007Date of Patent: May 22, 2012Assignees: Massachusetts Institute of Technology, Rutgers University, Research Foundation of State University of NYInventors: Bradley C. Kuszmaul, Michael A. Bender, Martin Farach-Colton
-
Publication number: 20110246503Abstract: A method, apparatus and computer program product for storing data in a disk storage system is presented. A high-performance dictionary data structure is defined. The dictionary data structure is stored on a disk storage system. Key-value pairs can be inserted and deleted into the dictionary data structure. Updates run faster than one insertion per disk-head movement. The structure can also be stored on any system with two or more levels of memory. The dictionary is high performance and supports with full transactional semantics, concurrent access from multiple transactions, and logging and recovery. Keys can be looked up with only a logarithmic number of transfers, even for keys that have been recently inserted or deleted. Queries can be performed on ranges of key-value pairs, including recently inserted or deleted pairs, at a constant fraction of the bandwidth of the disk.Type: ApplicationFiled: April 6, 2010Publication date: October 6, 2011Inventors: Michael A. Bender, Martin Farach-Colton, Yonatan R. Fogel, Zardosht Kasheff, Bradley C. Kuszmaul, Vincenzo Liberatore, Barry Perlman, Rich Prohaska, David S. Wells
-
Publication number: 20110191545Abstract: A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.Type: ApplicationFiled: April 11, 2011Publication date: August 4, 2011Inventors: Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson, Bradley C. Kuszmaul, Krste Asanovic
-
Patent number: 7925839Abstract: A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.Type: GrantFiled: July 7, 2008Date of Patent: April 12, 2011Assignee: Silicon Graphics InternationalInventors: Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson, Bradley C. Kuszmaul, Krste Asanovic
-
Publication number: 20080307181Abstract: A method, apparatus and computer program product for storing data in a disk storage system is presented. A dictionary data structure is defined and stored on the disk storage system. Key-value pairs can be inserted and deleted into the dictionary data structure, with full transactional semantics, at a rate that is faster than one insertion per disk-head movement. Keys can be looked up with only a logarithmic number of transfers, even for keys that have been recently inserted or deleted. Queries can be performed on ranges of key-value pairs, including recently inserted or deleted pairs, at a constant fraction of the bandwidth of the disk. The dictionary employs indirect logging for physical block logging.Type: ApplicationFiled: June 8, 2007Publication date: December 11, 2008Inventors: Bradley C. Kuszmaul, Michael A. Bender, Martin Farach-Colton
-
Patent number: 7398359Abstract: A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.Type: GrantFiled: April 30, 2004Date of Patent: July 8, 2008Assignee: Silicon Graphics, Inc.Inventors: Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson, Bradley C. Kuszmaul, Krste Asanovic
-
Publication number: 20040034678Abstract: The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path delays of many components in existing implementations grow quadratically with the issue width and the window size. This patent presents a novel way to reimplement these components and reduce their critical-path delay growth. It then describes an entire processor microarchitecture, called the Ultrascalar processor, that has better critical-path delay growth than existing superscalars. Most of our scalable designs are based on a single circuit, a cyclic segmented parallel prefix (cspp). We observe that processor components typically operate on a wrap-around sequence of instructions, computing some associative property of that sequence. For example, to assign an ALU to the oldest requesting instruction, each instruction in the instruction sequence must be told whether any preceding instructions are requesting an ALU.Type: ApplicationFiled: June 27, 2003Publication date: February 19, 2004Applicant: Yale UniversityInventors: Bradley C. Kuszmaul, Dana Sue Henry-Kuszmaul
-
Patent number: 6609189Abstract: The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path delays of many components in existing implementations grow quadratically with the issue width and the window size. This patent presents a novel way to reimplement these components and reduce their critical-path delay growth. It then describes an entire processor microarchitecture, called the Ultrascalar processor, that has better critical-path delay growth than existing superscalars. Most of our scalable designs are based on a single circuit, a cyclic segmented parallel prefix (cspp). We observe that processor components typically operate on a wrap-around sequence of instructions, computing some associative property of that sequence. For example, to assign an ALU to the oldest requesting instruction, each instruction in the instruction sequence must be told whether any preceding instructions are requesting an ALU.Type: GrantFiled: March 12, 1999Date of Patent: August 19, 2003Assignee: Yale UniversityInventors: Bradley C. Kuszmaul, Dana Sue Henry-Kuszmaul
-
Patent number: 5680550Abstract: A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and data communications operations in connection with commands. The processing elements also performing diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The command processor generates commands for the processing elements, and also performs diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The diagnostic processor generates diagnostic requests. The communication network includes three elements, including a data router, a control network and a diagnostic network. The data router is connected to the processing elements for facilitating the transfer of data among them during a data communications operation.Type: GrantFiled: February 13, 1995Date of Patent: October 21, 1997Assignee: TM Patents, LPInventors: Bradley C. Kuszmaul, Charles E. Leiserson, Shaw-Wen Yang, Carl R. Feynman, W. Daniel Hillis, David C. Douglas
-
Patent number: 5590283Abstract: A digital computer comprises a plurality of processing elements, a communications router, and a control network. Each processing element performs data processing operations in connection with commands, at least some of the processing elements performing the data processing operations in connection with the commands in messages they receive over the control network. Each processing element also generates and receives data transfer messages, each including an address portion containing an address, for transfer to another processing element as identified by the address. At least one of the processing elements further generates the control network messages for transfer over the communications router. The communications router comprises router nodes interconnected in the form of a "fat-tree," and the control network comprises control network nodes interconnected in the form of a tree, with the processing elements being connected at the leaf nodes of the respective communications router and control network.Type: GrantFiled: January 27, 1995Date of Patent: December 31, 1996Assignee: Thinking Machines CorporationInventors: W. Daniel Hillis, David C. Douglas, Charles E. Leiserson, Bradley C. Kuszmaul, Mahesh N. Ganmukhi, Jeffrey V. Hill, Monica C. Wong-Chan
-
Patent number: 5530809Abstract: A digital computer comprising a plurality of message generating nodes interconnected by a routing network. The routing network transfers messages among the message generating elements in accordance with address information identifying a destination message generating element. Each message generating node includes a message data generator and a network interface. The message data generator generates message data items each including an address data portion comprising a destination identifier. The network interface includes a message generator and an address translation table, the table including a plurality of entries identifying, for at least one destination identifier, a translated destination identifier. The message generator, in response to the receipt of a message data item from the message data generator, generates a message for transmission to the routing network.Type: GrantFiled: January 14, 1994Date of Patent: June 25, 1996Assignee: Thinking Machines CorporationInventors: David C. Douglas, Charles E. Leiserson, Bradley C. Kuszmaul, Shaw-Wen Yang, W. Daniel Hillis, David Wells, Carl R. Feynman, Bruce J. Walker, Brewster Kahle
-
Patent number: 5390298Abstract: A computer including a processor array and a routing network. Processors in the processor array generate messages for transfer to over the routing network, each message including a path identifier portion identifying a path from a source, message processor to a destination processor. The routing network comprises a plurality of interconnected router nodes, at least some of said router nodes being connected to the processors to receive messages therefrom and transmit messages thereto. Each router node operates in a plurality of modes. In a first mode, the router nodes couple received messages to a router node connected thereto in accordance with the path identifier portion to thereby transfer each respective message along the path identified in its path identifier portion.Type: GrantFiled: January 14, 1994Date of Patent: February 14, 1995Assignee: Thinking Machines CorporationInventors: Bradley C. Kuszmaul, Charles E. Leiserson, Shaw-Wen Yang, Carl R. Feynman, W. Daniel Hillis, David Wells, Cynthia J. Spiller