Patents by Inventor Bradley Coffman

Bradley Coffman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • IPS SOC PLL monitoring and error reporting
    Patent number: 11544160
    Abstract: The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Prashant D. Chaudhari, Michael N. Derr, Bradley Coffman, Arthur Jeremy Runyan, Gustavo Patricio Espinosa, Daniel James Knollmueller, Ivan Rodrigo Herrera Mejia
  • Functional safety system error injection technology
    Patent number: 10824529
    Abstract: Systems, apparatuses and methods may provide for technology that detects a startup of a system on chip (SoC) and injects, during the startup, one or more domain startup errors into a plurality of domains on the SoC. Additionally, the technology may determine whether the domain startup error(s) were detected during the startup. In one example, the plurality of domains include one or more fabric interfaces.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: November 3, 2020
    Assignee: Intel Corporation
    Inventors: Prashant Chaudhari, Michael Derr, Gustavo Espinosa, Balaji Vembu, Richard Shannon, Bradley Coffman, Daniel Knollmueller
  • IPS SOC PLL MONITORING AND ERROR REPORTING
    Publication number: 20200117554
    Abstract: The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.
    Type: Application
    Filed: June 28, 2019
    Publication date: April 16, 2020
    Inventors: Prashant D. Chaudhari, Michael N. Derr, Bradley Coffman, Arthur Jeremy Runyan, Gustavo Patricio Espinosa, Daniel James Knollmueller, Ivan Mejia Herrera
  • FUNCTIONAL SAFETY SYSTEM ERROR INJECTION TECHNOLOGY
    Publication number: 20190050308
    Abstract: Systems, apparatuses and methods may provide for technology that detects a startup of a system on chip (SoC) and injects, during the startup, one or more domain startup errors into a plurality of domains on the SoC. Additionally, the technology may determine whether the domain startup error(s) were detected during the startup. In one example, the plurality of domains include one or more fabric interfaces.
    Type: Application
    Filed: December 29, 2017
    Publication date: February 14, 2019
    Inventors: Prashant Chaudhari, Michael Derr, Gustavo Espinosa, Balaji Vembu, Richard Shannon, Bradley Coffman, Daniel Knollmueller