Abstract: A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.

Abstract: A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.

Abstract: A method, apparatus and computer instructions are provided to autonomically monitor and adjust system characteristics based on a customer optimization goal specified in a policy or profile. An autonomic management component is implemented in firmware comprising a set of control algorithms. Response to reading system characteristics from a plurality of sensors, the autononmic management component selects at least one control algorithm from the set and the control algorithm adjusts the parameters of the system characteristic to optimize performance according to the optimization goal specified by the customer.

Abstract: An apparatus and method for accurately tuning the speed of an integrated circuit, i.e. a computer chip, using a built-in sense circuit and controller are provided. The sense circuit is provided in association with a monitored path. The sense circuit includes a variable delay element coupled to a controller. A data signal from the monitored path is provided to the sense circuit which adds an amount of delay as determined by the controller to the data signal. The delayed data signal and the original data signal are compared to determine if their values match. If they match, then the amount of delay added by the variable delay element is increased. If they do not match, then a previous amount of delay, prior to the mismatch, is output as the slack of the monitored path. The slack may then be used to tune the speed of the integrated circuit.

Abstract: A method and system for increasing speeds of transferring data in a data transfer system which includes a data source and data sink. Both the data source and data sink include clocks which are synchronized to a common clock frequency. A buffer is provided at the data sink and this buffer is utilized to received data from the data source. A control circuit is provided at the data sink and this control circuit receives a bus clock signal from the data source. An N segment dynamic shift register is provided within the data sink which includes at least two segments. A selectable shift control is provided for passing the data through an M segment subset of the N segment shift register, where M is less than N. Additionally, the length of the M segment subset is determined by the phase of a clock within the data sink at the time which the bus clock signal from the data source is received at the data sink.

Abstract: A method and system for determining an initial architectural state for instruction trace reconstruction. Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyses and timing. One well-known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine instruction addresses, data addresses and data during the trace. However, the initial architectural state (the state of all caches, buffers and registers) must be determined in order to accurately reconstruct an instruction trace. At least one cache within the processor system is divided into two portions, the content of that cache is invalidated and each cache entry thereafter is duplicated within each portion of the divided cache.