Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.

Abstract: An electronic device includes a semiconductor substrate having a plurality of trenches formed therein. Each trench includes a sidewall having a doped region, a sidewall liner, and a filler material. The substrate has a slip density of less than 5 cm?2. The low slip density is achieved by a novel annealing protocol performed after implanting the dopant in the sidewall to repair damage and/or stress caused by the implant process.

Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.

Abstract: In some examples, a method includes etching a substrate to form a trench, wherein the trench includes sidewalls. The method further includes forming a first isolation region in the trench by growing a first layer of a first thickness on the sidewalls using a dry oxidation technique and depositing a second layer to fill a portion of the trench, the second layer contacting the first layer. The method further includes etching third and fourth layers atop the substrate to expose a first portion of the substrate. The method further includes growing a second isolation region in the substrate through the first portion by using a dry-wet-dry oxidation technique.

Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.

Abstract: An electronic device includes a semiconductor substrate having a plurality of trenches formed therein. Each trench includes a sidewall having a doped region, a sidewall liner, and a filler material. The substrate has a slip density of less than 5 cm?2. The low slip density is achieved by a novel annealing protocol performed after implanting the dopant in the sidewall to repair damage and/or stress caused by the implant process.

Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.

Abstract: A method for fabricating an integrated circuit (IC) includes etching trenches into a semiconductor surface of a substrate that has a mask thereon. Trench implanting using an angled implant then forms doped sidewalls of the trenches. Furnace annealing after trench implanting includes a ramp-up portion to a maximum peak temperature range of at least 975° C. and ramp-down portion, wherein the ramp-up portion is performed in a non-oxidizing ambient for at least a 100° C. temperature ramp portion with an O2 flow being less than 0.1 standard liter per minute (SLM). The sidewalls and a bottom of the trench are thermally oxidized to form a liner oxide after furnace annealing to form dielectric lined trenches. The dielectric lined trenches are filled with a fill material, and overburden portions of the fill material are then removed to form filled trenches.

Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.

Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.

Abstract: In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

Abstract: In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

Abstract: By controlling the concentration and size of bulk micro defects (BMD) during the manufacture of an integrated circuit slip and associated yield loss due to slip may be eliminated. A process for eliminating slip that is customized to an integrated circuit (IC) manufacturing flow is disclosed. The process is adapted to the oxygen content of the starting material and to the thermal budget of an IC manufacturing flow and generates a sufficient concentration of BMDs of a size that is optimized to getter microcracks thereby eliminating slip. Slip is eliminated in unpatterned wafers and in wafers containing shallow trench isolation and deep trench isolation using a BMD nucleation anneal and a BMD growth anneal.

Abstract: A method of semiconductor fabrication includes providing an unpatterned lightly doped Czochralski bulk silicon substrate (LDCBS substrate) having a concentration of oxygen atoms of at least (?) 1017 atoms/cm3 with a boron doping or n-type doping concentration of between 1×1012 cm?3 and 5×1014 cm?3. Before any oxidization processing, the LDCBS substrate is annealed at a nucleating temperature between 550° C. and 760° C. for a nucleating time that nucleates the oxygen atoms in a sub-surface region of the LDCBS substrate to form oxygen precipitates therefrom. After the annealing, a surface of the LDCBS substrate or an epitaxial layer on the surface of the LDCBS substrate is initially oxidized in an oxidizing ambient at a peak temperature of between 800° C. and 925° C. for a time less than or equal (?) to 30 minutes.

Abstract: A method for fabricating an integrated circuit (IC) includes initial oxidizing of a semiconductor surface of a substrate. The substrate is heated after the initial oxidizing using a plurality of furnace processing steps which each include a peak processing temperature between 800° C. and 1300° C. The furnace processing steps include at least one accelerated processing step having an accelerated ramp portion in a temperature range between 800° C. and 1250° C. providing an accelerated ramp-up rate and/or an |accelerated ramp-down rate| of at least (?) 5.5° C./min.

Abstract: A method of nucleating and growing oxygen precipitates during a pad oxidation process. The nucleating is performed during in the oxidation furnace prior to the pad oxide growth. At least a portion of the growth of the oxygen precipitates occurs during the pad oxide growth. The oxygen precipitates are of sufficient concentration and size in lightly doped p-type wafers for effective gettering of heavy metals is deep submicron transistor, integrated circuit manufacturing flows.

Abstract: A method for fabricating an integrated circuit (IC) includes initial oxidizing of a semiconductor surface of a substrate. The substrate is heated after the initial oxidizing using a plurality of furnace processing steps which each include a peak processing temperature between 800° C. and 1300° C. The furnace processing steps include at least one accelerated processing step having an accelerated ramp portion in a temperature range between 800° C. and 1250° C. providing an accelerated ramp-up rate and/or an |accelerated ramp-down rate| of at least (?) 5.5° C./min.

Abstract: A method of nucleating and growing oxygen precipitates of sufficient concentration and size in lightly doped p-type wafers for effective gettering of heavy metals is deep submicron transistor, integrated circuit manufacturing flows.