Abstract: A data-processing method and system generally comprises identifying a plurality of hardware resources associated with a data-processing apparatus, time-slicing the plurality of hardware resources. Thereafter the plurality of active hardware resources can be allocated among a plurality of active hardware resources associated with the data-processing apparatus, thereby allowing a limited number of hardware resources to service a larger number of physical devices associated with the data-processing apparatus. An appropriate hardware resource can be selected from among the plurality of active hardware resources utilizing one or more swapping algorithms.

Abstract: Methods and associated structures for bypassing virtual memory and memory mapping management features provided in a memory controller applied to simpler computing applications. In one aspect hereof, simpler, embedded computing applications may utilize standard memory controllers including cash management and memory component interfacing features but may bypass virtual memory management features within the same memory controller component. Rather, features and aspects hereof intercept memory accesses generated by the memory controller for address translation features and perform simpler address substitution to apply an appropriate translated address to the system bus.

Abstract: A data-processing method and system generally comprises identifying a plurality of hardware resources associated with a data-processing apparatus, time-slicing the plurality of hardware resources. Thereafter the plurality of active hardware resources can be allocated among a plurality of active hardware resources associated with the data-processing apparatus, thereby allowing a limited number of hardware resources to service a larger number of physical devices associated with the data-processing apparatus. An appropriate hardware resource can be selected from among the plurality of active hardware resources utilizing one or more swapping algorithms.

Abstract: A method, apparatus, and processor instructions for processing commands in a small computer system interface controller. A current command is received from a host in which the current command is associated with a first target identifier. A determination is made as to whether a subsequent command is available after the current command. A determination is also made as to whether the first target identifier matches a second target identifier and is associated with the subsequent command. The current command is batched with the subsequent command if the first target identifier matches the second target identifier in which case the current command and the subsequent command are sent using a single connection. The comparing of target IDs and combining of commands continue until no further messages are available or until a match between target identifiers is absent. At that time, the batched messages are sent to the target.