Abstract: According to one general aspect, an apparatus may include a context-specific encryption key circuit configured to generate a key value, wherein the key value is specific to a context of a set of instructions. The apparatus may include a target address prediction circuit configured to provide a target address for a next instruction in the set of instructions. The apparatus may include a target address memory configured to store an encrypted version of the target address, wherein the target address is encrypted using, at least in part, the key value. The apparatus may further include an instruction fetch circuit configured to decrypt the target address using, at least in part, the key value, and retrieve the target address.

Abstract: Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.

Abstract: Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.

Abstract: An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value to establish security verification of secure software within the secure memory environment.

Abstract: An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value in order to establish security verification of secure software within the secure memory environment.

Abstract: A cache way replacement technique to identify and replace a least-recently used cache way. A cache way replacement technique in which a least-recently used cache way is identified and replaced, such that the replacement of cache ways over time is substantially evenly distributed among a set of cache ways in a cache memory. A least-recently used cache way is identified in a cache memory having a non-binary number of cache ways.

Abstract: A cache way replacement technique to identify and replace a least-recently used cache way. A cache way replacement technique in which a least-recently used cache way is identified and replaced, such that the replacement of cache ways over time is substantially evenly distributed among a set of cache ways in a cache memory. A least-recently used cache way is identified in a cache memory having a non-binary number of cache ways.

Abstract: A system and method for permitting the execution of system management mode (SMM) code during secure operations in a microprocessor system is described. In one embodiment, the system management interrupt (SMI) may be first directed to a handler in a secured virtual machine monitor (SVMM). The SMI may then be re-directed to SMM code located in a virtual machine (VM) that is under the security control of the SVMM. This redirection may be accomplished by allowing the SVMM to read and write the system management (SM) base register in the processor.

Abstract: An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value in order to establish security verification of secure software within the secure memory environment.

Abstract: The present invention is directed to a system and method for implementing a re-ordered instruction cache. In one embodiment, groups or “packets” of instructions with specific packet sizes are formed. Each of packets includes two or more positions. The two or more positions are defined such that they support one or more different types of instructions. Each of the positions are also correlated to a subset of the specialized execution units of the processor. Given a specific packet size and definitions for each of the positions, each of the instructions are re-ordered according to instruction type and loaded into the instruction cache in the new order.

Abstract: A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.

Abstract: The present invention is directed to a system and method for implementing a re-ordered instruction cache. In one embodiment, groups or “packets” of instructions with specific packet sizes are formed. Each of packets includes two or more positions. The two or more positions are defined such that they support one or more different types of instructions. Each of the positions are also correlated to a subset of the specialized execution units of the processor. Given a specific packet size and definitions for each of the positions, each of the instructions are re-ordered according to instruction type and loaded into the instruction cache in the new order.

Abstract: An apparatus and method for loading instructions into a trace cache line using instruction packetization to increase the throughput of instructions through a given rename unit. The present invention uses the properties of the particular sequence of instructions to eliminate the redundant allocation of source and destination registers which may increase the number of instructions that can be processed simultaneously without increasing the size or complexity of the rename unit.

Abstract: A data processing system includes a data processor (10) coupled to a memory system having a first memory, such as an L1 data cache (16), arranged with a second memory (such as an L2 cache) at a lower hierarchical level. The data processor (10) prefetches data elements of a vector into the first memory prior to processing such data elements. If a requested data element is not present in the first memory, a load request is issued to the second memory and to lower levels of the memory hierarchy until the requested data element is finally retrieved and stored in the first memory. The data processor (10) continues to prefetch subsequent data elements of the vector by considering the length of the data element and the stride of the vector. In one embodiment, the data processor (10) prefetches the vector into the first memory in response to a single data stream touch load (DST) instruction (100).

Abstract: A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.

Abstract: When a request to branch to an address stored in a return memory location (440) occurs, a busy bit is used to determine whether the return memory location (440) contains updated information. When the information is not updated, a predicted address is provided to the prediction verifier (460) by the link stack (410). Once the busy bit is valid, the prediction verifier (460) determines if a proper prediction was made. When an improper prediction was made, the update portion (415) of the link stack (410) based on information from the comparator (425) determines if a value stored in the link stack (410) matches the value stored in the return memory location (440). The link stack (410) is synchronized based upon a favorable comparison indicating the return memory location value matches a value in the link stack. If a match is not found, the predicted address is placed back on the link stack or alternatively the link stack is cleared.

Abstract: A data processor has first calculation circuitry (26), a rename buffer (34), and a queue (36). The first calculation circuitry generates a first and a second result from supplied operands and received programmed instructions. The rename buffer is coupled to the first calculation circuitry and stores a series of first results received from the first calculation circuitry. The rename buffer outputs the series of first results to a first predetermined register. The queue is also coupled to the first calculation circuitry and stores a series of second results. The queue outputs the sequence of second results to a second predetermined register in the same the sequence as it received the second results from the first calculation circuitry.

Abstract: An integrated circuit microprocessor has on-board programmable chip select logic. Each of several chip select outputs is individually programmable by means of one or more control register bit fields. For instance, each chip select is asserted for bus cycles within an address range whose starting address and block size are both programmable. In addition, each chip select can be programmed to be active on read cycles only, on write cycles only, or on both read and write cycles. Each chip select can be programmed to be active during interrupt acknowledge cycles only if the interrupt being acknowledged has the same priority level as has been programmed for that chip select. In addition, the timing of the assertion of each chip select is programmable to coincide with either the address strobe or data strobe of the bus cycle. The chip select logic is designed so that it is configured to come out of reset by producing an active chip select signal during the first bus cycle run by the processor following the reset.

Abstract: A result normalizer (58) for use with an adder (56) generates a mask in two stages that indicates the location of the leading one in the adder result. In the first stage, a leading zero anticipator (68) determines the position to within two digits. In the second stage, a count leading zero indicator (70) determines the position to a single digit. The mask is used to control the number of digits that each stage of a multiplexer array (66) shifts the adder result. The output of the multiplexer array thereby contains a leading one. The result normalizer may be advantageously used in high performance applications such as in a floating point execution unit in a data processor or in digital signal processing systems.

Abstract: A digital computing system having a low power mode of operation includes a mechanism for communicating, prior to entering the low power mode, information determinative of which events shall be capable of causing the termination of the low power mode. An integrated circuit microcomputer enters a low power mode in response to executing an LPSTOP instruction. Only reset events and those interrupt events having a priority level sufficiently high to pass an interrupt mask are capable of causing the termination of the low power mode. The LPSTOP instruction causes immediate data to be loaded into a status register, resetting the interrupt mask bits. The interrupt mask is then written, by means of a special bus cycle, into an interrupt mask register in a sub-system within the microcomputer. This subsystem then shuts down the clock signals to the remainder of the microcomputer, leaving only this sub-system active.