Abstract: A bypass system and method that mimics read timing of a memory system which includes a self-timing circuit and a sense amplifier. When prompted, the self-timing circuit initiates the sense amplifier to evaluate its differential input. The bypass system includes a memory controller that is configured to provide a bypass enable, to prompt the self-timing circuit, and to disable normal read control when a bypass read operation is indicated. A bypass latch latches an input data value, converts the input data value into an input complementary pair, and provides the complementary pair to the differential input of the sense amplifier. The sense amplifier, when initiated, evaluates the input complementary pair after its self-timing period and provides an output data value. The bypass latch and self-timing circuit may operate synchronous with a read clock in a read domain of the memory for more accurate memory read timing.

Abstract: A bypass system and method that mimics read timing of a memory system which includes a self-timing circuit and a sense amplifier. When prompted, the self-timing circuit initiates the sense amplifier to evaluate its differential input. The bypass system includes a memory controller that is configured to provide a bypass enable, to prompt the self-timing circuit, and to disable normal read control when a bypass read operation is indicated. A bypass latch latches an input data value, converts the input data value into an input complementary pair, and provides the complementary pair to the differential input of the sense amplifier. The sense amplifier, when initiated, evaluates the input complementary pair after its self-timing period and provides an output data value. The bypass latch and self-timing circuit may operate synchronous with a read clock in a read domain of the memory for more accurate memory read timing.

Abstract: A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.

Abstract: A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.

Abstract: A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.

Abstract: A sense amplifier (11) and method for sensing a MRAM cell (77) is provided. The sense amplifier (11) includes a precharge circuit (13?) having an operational amplifier (40, 42) that uses a voltage divider (115, 116) in a feedback path to control the amount of charge stored on a capacitor (104, 105). During a precharge portion of a read operation, the charge stored on the capacitor (104, 105) is used to precharge the sense amplifier (11). By using charge sharing to precharge the sense amplifier (11), the sense amplifier (11) can be precharged to a steady state common mode voltage more quickly, thus decreasing time required for a read operation.

Abstract: An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.

Abstract: A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.

Abstract: A circuit provides a stress voltage to magnetic tunnel junctions (MTJs), which comprise the storage elements of a magnetoresitive random access memory (MRAM), during an accelerated life test of the MRAM. The stress voltage is selected to provide a predetermined acceleration of aging compared to normal operation. A source follower circuit is used to apply a stress voltage to a subset of the memory cells at given point in time during the life test. The stress voltage is maintained at the desired voltage by a circuit that mocks the loading characteristics of the portion of the memory array being stressed. The result is a closely defined voltage applied to the MTJs so that the magnitude of the acceleration is well defined for all of the memory cells.

Abstract: An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.

Abstract: An integrated circuit (101) includes electrical circuitry (105) formed on a substrate (103). An interconnect layer (109, 117) is formed over the electrical circuitry (105). In one example, a plurality of magneto-resistive random access memory cells (MRAM) (161, 171) is implemented above the interconnect layer. Each of the MRAM cells comprises a magneto-resistive tunnel junction (MTJ) storage element. A transistor (130) is formed-over the interconnect layer (109, 117). In one embodiment, the transistor is implemented as a thin film transistor (TFT). In one embodiment the transistor is a select transistor and may be coupled to one or more of the MTJ storage elements. Access circuitry (203, 205, 207, 209) is formed on the substrate (103) under the plurality of MRAM cells (161, 171).

Abstract: An integrated circuit (101) includes electrical circuitry (105) formed on a substrate (103). An interconnect layer (109, 117) is formed over the electrical circuitry (105). In one example, a plurality of magneto-resistive random access memory cells (MRAM) (161, 171) is implemented above the interconnect layer. Each of the MRAM cells comprises a magneto-resistive tunnel junction (MTJ) storage element. A transistor (130) is formed over the interconnect layer (109, 117). In one embodiment, the transistor is implemented as a thin film transistor (TFT). In one embodiment the transistor is a select transistor and may be coupled to one or more of the MTJ storage elements. Access circuitry (203, 205, 207, 209) is formed on the substrate (103) under the plurality of MRAM cells (161, 171).

Abstract: A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.

Abstract: An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.

Abstract: An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.

Abstract: The state of a MRAM cell is detected when the magnetic tunnel junction (MTJ) of the MRAM cell has a reduced bias from the maximum voltage that is used for biasing. In one example, the MTJ of the selected cell and the MTJ of a reference cell are both biased to a first voltage. The MTJs then discharge this bias asymptotically (RC time constant based utilizing bit line capacitance and MTJ resistance) to a lower voltage such as ground but at rates that are different for the selected cell versus the reference cell due to MTJ resistance differential. At a predetermined time the voltage differential is detected. In another example, the MTJs are precharged to a low voltage then are driven asymptotically toward a higher voltage. Thus, at the time of sensing for both cases, the voltage across the MTJ is less than the bias voltage that is being used.

Abstract: The state of a MRAM cell is detected when the magnetic tunnel junction (MTJ) of the MRAM cell has a reduced bias from the maximum voltage that is used for biasing. In one example, the MTJ of the selected cell and the MTJ of a reference cell are both biased to a first voltage. The MTJs then discharge this bias asymptotically (RC time constant based utilizing bit line capacitance and MTJ resistance) to a lower voltage such as ground but at rates that are different for the selected cell versus the reference cell due to MTJ resistance differential. At a predetermined time the voltage differential is detected. In another example, the MTJs are precharged to a low voltage then are driven asymptotically toward a higher voltage. Thus, at the time of sensing for both cases, the voltage across the MTJ is less than the bias voltage that is being used.

Abstract: In a memory, a bias circuit (112, 212, 312, 412) uses a current reference (108) for providing a reference current and control circuitry (106, 120) to bias a sense amplifier (114) with a varying voltage (VB). The varying voltage maintains current through MRAM bit cells (177-179) at a value proportional to the reference current over variations in average bit cell resistance with immunity to variations in process, supply voltage and temperature. In one form, a mock sense amplifier (122, 126, 132, 134) and mock array of bit cells (130, 136) are used to establish internal steady state voltages equivalent to a steady state condition of the sense amplifier with equalized outputs and to generate the varying bias voltage. Matching diode-connected transistors in each of the control circuitry and either the mock sense amplifier or the sense amplifier is used to generate the varying bias voltage.

Abstract: A MRAM toggle type memory cell is read by first providing a first signal representative of the initial state to a sense amplifier (1300, 1500). A resistance of the cell is temporarily changed by altering a magnetic polarization of the free layer of the cell. A second signal responsive to altering the resistance of the MRAM cell is provided to the sense amplifier (1300, 1500). The first signal is compared to the second signal to determine the state of the MRAM cell.

Abstract: A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.