Patents by Inventor Bradley J Larsen
Bradley J Larsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8759903Abstract: A method of increasing the radiation hardness of a semiconductor device using a modified high density plasma oxide (MHDPDX) film is described. In the method a high density plasma (HDP) process is used to deposit the MHDPDX film. During the HDP process, the silicon source gas to oxygen source gas ratio is chosen so as to deposit an excess silicon content within the MHDPDX film. The MHDPDX film is then annealed to cause the excess silicon to migrate and amalgamate, creating silicon nanoclusters having an average size of about 3-5 nm. The rad-hard properties of conventional BPSG films and various MHDPDX films are then compared.Type: GrantFiled: September 1, 2006Date of Patent: June 24, 2014Assignee: Honeywell International Inc.Inventors: Michael S Liu, David J Swanson, Bradley J Larsen
-
Patent number: 8399845Abstract: Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.Type: GrantFiled: March 19, 2012Date of Patent: March 19, 2013Assignee: Honeywell International Inc.Inventors: Paul S. Fechner, David O. Erstad, Todd A. Randazzo, Bradley J. Larsen
-
Publication number: 20130049215Abstract: In one example, an integrated circuit includes a silicon on insulator (SOI) substrate including a plurality transistors disposed in a layer of the SOI substrate and a base oxide layer disposed on a first side of the layer. The integrated circuit also may include a first interconnect formed on the first side of the layer, and the first interconnect may electrically connect a first transistor of the plurality of transistors and a second transistor of the plurality of transistors. Additionally, the integrated circuit may include a second interconnect formed on a second side of the layer opposite the first side of the layer, and the second interconnect may electrically connect a third transistor of the plurality of transistors and a fourth transistor of the plurality of transistors.Type: ApplicationFiled: August 30, 2011Publication date: February 28, 2013Applicant: Honeywell International Inc.Inventor: Bradley J. Larsen
-
Patent number: 8310021Abstract: A method of manufacturing a neutron detector comprises forming a first wafer by at least forming an oxide layer on a substrate, forming an active semiconductor layer on the oxide layer, and forming an interconnect layer on the active semiconductor layer, forming at least one electrically conductive pathway extending from the interconnect layer through the active semiconductor layer and the oxide layer, forming a circuit transfer bond between the interconnect layer and a second wafer, removing the substrate of the first wafer after forming the circuit transfer bond, depositing a bond pad on the oxide layer after removing the substrate of the first wafer, wherein the bond pad is electrically connected to the electrically conductive pathway, depositing a barrier layer on the oxide layer after removing the substrate of the first wafer, and depositing a neutron conversion layer on the barrier layer after depositing the barrier layer.Type: GrantFiled: July 13, 2010Date of Patent: November 13, 2012Assignee: Honeywell International Inc.Inventors: Bradley J. Larsen, Todd A. Randazzo
-
Publication number: 20120228513Abstract: Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.Type: ApplicationFiled: March 19, 2012Publication date: September 13, 2012Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Paul S. Fechner, David O. Erstad, Todd A. Randazzo, Bradley J. Larsen
-
Patent number: 8153985Abstract: Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.Type: GrantFiled: August 6, 2009Date of Patent: April 10, 2012Assignee: Honeywell International Inc.Inventors: Todd Andrew Randazzo, Bradley J. Larsen, Paul S. Fechner
-
Publication number: 20120012957Abstract: A method of manufacturing a neutron detector comprises forming a first wafer by at least forming an oxide layer on a substrate, forming an active semiconductor layer on the oxide layer, and forming an interconnect layer on the active semiconductor layer, forming at least one electrically conductive pathway extending from the interconnect layer through the active semiconductor layer and the oxide layer, forming a circuit transfer bond between the interconnect layer and a second wafer, removing the substrate of the first wafer after forming the circuit transfer bond, depositing a bond pad on the oxide layer after removing the substrate of the first wafer, wherein the bond pad is electrically connected to the electrically conductive pathway, depositing a barrier layer on the oxide layer after removing the substrate of the first wafer, and depositing a neutron conversion layer on the barrier layer after depositing the barrier layer.Type: ApplicationFiled: July 13, 2010Publication date: January 19, 2012Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Bradley J. Larsen, Todd A. Randazzo
-
Publication number: 20110186940Abstract: A semiconductor device comprises a substrate, an active semiconductor layer situated on the substrate, a stack of interconnect layers deposited on the active semiconductor layer, and a neutron conversion layer deposited on the stack of interconnect layers, wherein the stack of interconnect layers is configured such that at least about 10% of secondary charged particles generated in the neutron conversion layer will have a sufficient ion track length in the active semiconductor layer to generate a detectable charge in the active semiconductor layer. Another semiconductor device comprises a substrate, an active semiconductor layer situated on the substrate, a neutron conversion layer deposited on the active semiconductor layer, and a stack of interconnect layers deposited on the neutron conversion layer.Type: ApplicationFiled: February 3, 2010Publication date: August 4, 2011Applicant: Honeywell International Inc.Inventors: Todd Andrew Randazzo, Bradley J. Larsen, Paul S. Fechner
-
Publication number: 20110089331Abstract: Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.Type: ApplicationFiled: August 6, 2009Publication date: April 21, 2011Applicant: Honywell International Inc.Inventors: Todd Andrew Randazzo, Bradley J. Larsen, Paul S. Fechner
-
Publication number: 20100200918Abstract: A CMOS memory element comprising silicon-on-insulator MOSFET transistors is disclosed wherein at least one of the MOSFET transistors is configured such that the body of the transistor is not connected to a voltage source and is instead permitted to electrically float. Implementations of the disclosed memory element with increased immunity to errors caused by heavy ion radiation are also disclosed.Type: ApplicationFiled: February 10, 2009Publication date: August 12, 2010Applicant: Honeywell International Inc.Inventors: Bradley J. Larsen, Todd A. Randazzo, Cheisan Yue
-
Patent number: 7679139Abstract: Non-planar SOI devices that include an “area-efficient” body tie are disclosed. The device includes a bulk substrate, an insulator layer formed on a surface of the bulk substrate, and a silicon body formed on a surface of the insulator layer. The silicon body preferably includes (i) a non-planar channel connecting a source region and a drain region, and (ii) a body tie that is adjacent to the channel and couples the channel to a voltage potential. The device further includes a gate dielectric formed on the channel and a gate material formed on the gate dielectric.Type: GrantFiled: September 11, 2007Date of Patent: March 16, 2010Assignee: Honeywell International Inc.Inventors: Bradley J. Larsen, Michael S. Liu, Paul S. Fechner
-
Publication number: 20100006912Abstract: A complementary metal-oxide-semiconductor (CMOS) static random-access-memory (SRAM) element comprising a planar metal-insulator-metal (MIM) capacitor is disclosed, and the planar MIM capacitor is electrically connected to the transistors in the CMOS memory element to reduce the effects of charged particle radiation on the CMOS memory element. Methods for immunizing a CMOS SRAM element to the effects of charged particle radiation are also disclosed, along with methods for manufacturing CMOS SRAM including planar MIM capacitors as integrated circuits.Type: ApplicationFiled: February 10, 2009Publication date: January 14, 2010Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Bradley J. Larsen, Todd A. Randazzo, Cheisan Yue
-
Publication number: 20090065866Abstract: Non-planar SOI devices that include an “area-efficient” body tie are disclosed. The device includes a bulk substrate, an insulator layer formed on a surface of the bulk substrate, and a silicon body formed on a surface of the insulator layer. The silicon body preferably includes (i) a non-planar channel connecting a source region and a drain region, and (ii) a body tie that is adjacent to the channel and couples the channel to a voltage potential. The device further includes a gate dielectric formed on the channel and a gate material formed on the gate dielectric.Type: ApplicationFiled: September 11, 2007Publication date: March 12, 2009Applicant: Honeywell International Inc.Inventors: Bradley J. Larsen, Michael S. Liu, Paul S. Fechner
-
Patent number: 7378705Abstract: An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell and a method of operation are disclosed for creating an EEPROM memory cell in a standard CMOS process. A single polysilicon layer is used in combination with lightly doped MOS capacitors. The lightly doped capacitors employed in the EEPROM memory cell can be asymmetrical in design. Asymmetrical capacitors reduce area. Further capacitance variation caused by inversion can also be reduced by using multiple control capacitors. In addition, the use of multiple tunneling capacitors provides the benefit of customized tunneling paths.Type: GrantFiled: September 1, 2005Date of Patent: May 27, 2008Assignee: Honeywell International, Inc.Inventors: James E. Riekels, Thomas B. Lucking, Bradley J. Larsen, Gary R. Gardner
-
Patent number: 7177489Abstract: The present invention provides silicon based thin-film structures that can be used to form high frequency optical modulators. Devices of the invention are formed as layered structures that have a thin-film dielectric layer, such as silicon dioxide, sandwiched between silicon layers. The silicon layers have high free carrier mobility. In one aspect of the invention a high mobility silicon layer can be provided by crystallizing an amorphous silicon layer. In another aspect of the invention, a high mobility silicon layer can be provided by using selective epitaxial growth and extended lateral overgrowth thereof.Type: GrantFiled: August 10, 2004Date of Patent: February 13, 2007Assignee: Honeywell International, Inc.Inventors: Thomas Keyser, Cheisan J. Yue, Bradley J. Larsen
-
Patent number: 6890832Abstract: A radiation-hardened STI process includes implanting a partially formed wafer with a fairly large dose (1013 to 1017 ions/cm2) of a large atom group III element, such as B, Al, Ga or In at an energy between about 30 and 500 keV. The implant is followed by an implant of a large group V element, such as P, As, Sb, or Bi using similar doses and energies to the group III element. The group V element compensates the group III element. The combination of the two large atoms decreases the diffusivity of small atoms, such as B, in the implanted areas. Furthermore, the combination of the group III and group V elements in roughly equal proportions creates recombination sites and electron traps in the field oxide, resulting in a radiation hardened semiconductor device.Type: GrantFiled: November 12, 2002Date of Patent: May 10, 2005Assignee: Aeroflex UTMC Microelectronic Systems, Inc.Inventors: David B. Kerwin, Bradley J Larsen
-
Patent number: 6828212Abstract: A method for fabricating a shallow trench isolation structure is described, in which a bottom pad oxide layer, a middle silicon nitride layer, a middle oxide layer and a top silicon nitride layer are sequentially formed on a silicon substrate. Photolithographic masking and anisotropic etching are then conducted to form a trench in the substrate. An oxide material is then deposited on top of the top silicon nitride layer, filling up the trenches at the same time. A chemical mechanical polishing step is then employed to remove the oxide material by using the top silicon nitride layer as a barrier layer. The top silicon nitride layer is then removed, followed by an isotropic etch of the oxide layer below. With the middle nitride layer acting as a natural etch stop, the oxide material is sculpted to a desirable shape. The middle nitride layer and the pad oxide layer are subsequently removed to complete the fabrication of a shallow trench isolation structure.Type: GrantFiled: October 22, 2002Date of Patent: December 7, 2004Assignee: Atmel CorporationInventors: Timothy M. Barry, Nicolas Degors, Donald A. Erickson, Amit S. Kelkar, Bradley J. Larsen
-
Publication number: 20040087104Abstract: A method for fabricating a shallow trench isolation structure is described, in which a bottom pad oxide layer, a middle silicon nitride layer, a middle oxide layer and a top silicon nitride layer are sequentially formed on a silicon substrate. Photolithographic masking and anisotropic etching are then conducted to form a trench in the substrate. An oxide material is then deposited on top of the top silicon nitride layer, filling up the trenches at the same time. A chemical mechanical polishing step is then employed to remove the oxide material by using the top silicon nitride layer as a barrier layer. The top silicon nitride layer is then removed, followed by an isotropic etch of the oxide layer below. With the middle nitride layer acting as a natural etch stop, the oxide material is sculpted to a desirable shape. The middle nitride layer and the pad oxide layer are subsequently removed to complete the fabrication of a shallow trench isolation structure.Type: ApplicationFiled: October 22, 2002Publication date: May 6, 2004Inventors: Timothy M. Barry, Nicolas Degors, Donald A. Erickson, Amit S. Kelkar, Bradley J. Larsen
-
Patent number: 5583380Abstract: A contact of large dimensions having a stringer strongly adhered to a contact hole's sidewalls. The contact hole is made to have a patterned perimeter having grooves protruding outward. The grooves have a size equal to a minimum contact dimension in at least one direction so as to ensure good step coverage into the groove areas. The grooves serve to anchor the stringer to the contact hole sidewalls by increasing the sidewall's surface area which increases adhesion, distributing stress from the stringer to the groove areas, and providing grooves with good step coverage.Type: GrantFiled: July 11, 1995Date of Patent: December 10, 1996Assignee: Atmel CorporationInventors: Bradley J. Larsen, Kurt Schertenleib
-
Patent number: RE36777Abstract: An apparatus and method for integrating a submicron CMOS device and a non-volatile memory, wherein a thermal oxide layer is formed over a semiconductor substrate and a two layered polysilicon non-volatile memory device formed thereon. A portion of the thermal oxide is removed by etching, a thin gate oxide and a third layer of polysilicon having a submicron depth is deposited onto the etched region. The layer of polysilicon is used as the gate for the submicron CMOS device. In so doing a submicron CMOS device may be formed without subjecting the device to the significant re-oxidation required in formation processes for dual poly non-volatile memory devices such as EPROMs and EEPROMs, and separate device optimization is achieved.Type: GrantFiled: October 7, 1998Date of Patent: July 11, 2000Assignee: Atmel CorporationInventors: Bradley J. Larsen, Todd A. Randazzo, Donald A. Erickson