Abstract: The present invention is directed to a circulator/isolator device that includes a housing having a substantially planar base portion integrally connected to a segmented flexible wall structure extending in a direction normal thereto. The substantially planar base portion and the segmented flexible wall structure forms an interior housing volume having a predetermined geometry. The segmented flexible wall structure includes a plurality of port apertures disposed therein. The plurality of port apertures are separated from each other and disposed at predetermined locations in the segmented flexible wall structure. A central stack is disposed within the interior housing volume at a predetermined position on the base portion. The central stack includes a substantially flat conductor having a plurality of port structures extending therefrom. Each of the plurality of port structures are disposed at predetermined positions at a perimeter portion of the substantially flat conductor.

Abstract: The present invention is directed to a circulator/isolator device that includes a housing having a substantially planar base portion integrally connected to a segmented flexible wall structure extending in a direction normal thereto. The substantially planar base portion and the segmented flexible wall structure forms an interior housing volume having a predetermined geometry. The segmented flexible wall structure includes a plurality of port apertures disposed therein. The plurality of port apertures are separated from each other and disposed at predetermined locations in the segmented flexible wall structure. A central stack is disposed within the interior housing volume at a predetermined position on the base portion. The central stack includes a substantially flat conductor having a plurality of port structures extending therefrom. Each of the plurality of port structures are disposed at predetermined positions at a perimeter portion of the substantially flat conductor.

Abstract: A method and apparatus are provided for recycling power in an integrated circuit. The integrated circuit includes a plurality of nets and a switched capacitor network. The plurality of nets includes a first logic net having a tendency to repetitively switch between logic high and low states during normal operation of the integrated circuit. The switched capacitor network includes a plurality of capacitors, which are selectively decoupled from the plurality of nets, selectively coupled to the first logic net in parallel with one another, and selectively coupled to at least one of the nets in series with one another.

Abstract: A design system for modeling bi-directional pad cells, the interaction of internal pull cells/resistors with pad cells of all types, and the interaction of external pull cells/resistors with pad cells of all types. This modeling technique involves the use of three separate pins on each bi-directional pad cell: an input-only pin, an output-only pin, and a resolved pin. The input-only pin reflects the data that is supplied to the pad from external sources. The output-only pin reflects the data that is supplied as output from the pad cell (strong data from the output driver). The resolved pin reflects the combination of the input and the output data that are present, as well as the effect of resistive data supplied by pull-up/down resistors/cells. The output-only and resolved pins are implemented as internal or hidden pins within a pad cell model. These pins are included in the model for the I/O pad cells in a given library. The existing pad pin serves as the input-only pin.

Abstract: A design system for modeling bi-directional pad cells, the interaction of internal pull cells/resistors with pad cells of all types, and the interaction of external pull cells/resistors with pad cells of all types. This modeling technique involves the use of three separate pins on each bi-directional pad cell: an input-only pin, an output-only pin, and a resolved pin. The input-only pin reflects the data that is supplied to the pad from external sources. The output-only pin reflects the data that is supplied as output from the pad cell (strong data from the output driver). The resolved pin reflects the combination of the input and the output data that are present, as well as the effect of resistive data supplied by pull-up/down resistors/cells. The output-only and resolved pins are implemented as internal or hidden pins within a pad cell model. These pins are included in the model for the I/O pad cells in a given library. The existing pad pin serves as the input-only pin.