Abstract: A variable precedence priority encoder apparatus is provided having a plurality of inputs, each receiving a corresponding bit of an input vector, and a like plurality of outputs. Each output is associated with a corresponding one of the plurality of inputs, thereby forming a plurality of input/output pairs. The encoder circuit also includes a priority assignment circuit coupling each input of the plurality of inputs to its associated corresponding output of the plurality of outputs. The priority assignment circuit assigns a priority to each input/output pair, such that an output, which corresponds to an input which receives an asserted bit, and which has a highest priority, provides an asserted bit while all other outputs provide bits that are not asserted. The priority assigned to each input can be dynamically updated within the priority assignment circuit. Updates of priority that shift the priority position by one or more inputs can be done all using the same circuit.

Abstract: A variable precedence priority encoder apparatus is provided having a plurality of inputs, each receiving a corresponding bit of an input vector, and a like plurality of outputs. Each output is associated with a corresponding one of the plurality of inputs, thereby forming a plurality of input/output pairs. The encoder circuit also includes a priority assignment circuit coupling each input of the plurality of inputs to its associated corresponding output of the plurality of outputs. The priority assignment circuit assigns a priority to each input/output pair, such that an output, which corresponds to an input which receives an asserted bit, and which has a highest priority, provides an asserted bit while all other outputs provide bits that are not asserted. The priority assigned to each input can be dynamically updated within the priority assignment circuit. Updates of priority that shift the priority position by one or more inputs can be done all using the same circuit.