Patents by Inventor Bradley Jensen
Bradley Jensen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10043716Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.Type: GrantFiled: August 22, 2016Date of Patent: August 7, 2018Assignee: Altera CorporationInventors: Dustin Do, Andy L. Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
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Publication number: 20160358825Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.Type: ApplicationFiled: August 22, 2016Publication date: December 8, 2016Applicant: Altera CorporationInventors: Dustin Do, Andy L. Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
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Patent number: 9449962Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.Type: GrantFiled: August 4, 2011Date of Patent: September 20, 2016Assignee: Altera CorporationInventors: Dustin Do, Andy L. Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
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Patent number: 9196749Abstract: A programmable device with a metal oxide semiconductor field effect transistor (MOSFET) surrounded by a programmable substrate region is described. The MOSFET has a source and drain region separated by a channel region with an insulating region and gate disposed above the channel region. A junction disposed within the substrate region controls the programmable substrate region. Biasing the junction depletes the substrate region, which isolates the body of the MOSFET from a secondary well. When the junction is left unbiased, the body of the MOSFET is electrically coupled to the secondary well.Type: GrantFiled: December 30, 2011Date of Patent: November 24, 2015Assignee: Altera CorporationInventors: Charu Sardana, Albert Ratnakumar, Qi Xiang, Bradley Jensen
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Patent number: 8878296Abstract: Integrated circuits with electrostatic discharge (ESD) protection circuitry are provided. The ESD protection circuitry does not include polysilicon resistors. The ESD protection circuitry may include n-channel transistors coupled in parallel between an output node that is connected to an input/output pin and a ground terminal. The n-channel transistors may each have a drain terminal that is coupled to the output node through first metal paths and a source terminal that is coupled to the ground terminal through second metal paths. The first and second metal paths may be routed over gate terminals of the respective n-channel transistors to provide sufficient resistance. The first and second metal paths may provide desired pull-down resistance in the ESD protection circuitry so that the ESD protection circuitry can sink sufficient current through each of the n-channel transistors to protect internal circuitry from damage in an ESD event.Type: GrantFiled: October 22, 2010Date of Patent: November 4, 2014Assignee: Altera CorporationInventors: Bradley Jensen, Charles Y. Chu
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Publication number: 20140032274Abstract: A system for managing dynamic pricing for online sales. The system includes a server to operate a commerce manager, a commerce manager, and a client. The server includes a processing device and a memory. The commerce manager includes a dynamic price manager operating on the processing device of the server to dynamically generate a price for a product. The dynamic price manager is influenced by market cues. The price is generated at a predetermined time interval. The client interacts with the commerce manager and is in communication with the server via a network. The client displays the price.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Applicant: TIKR, INC.Inventors: Todd Bradley Jensen, Kevin Alan Neilson, Paul Lydolph, III
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Patent number: 8614130Abstract: Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may include first, second, and third regions. The first and third regions may include p-wells. The second region may include an n-well. Stripes of diffusion regions may be formed at the surface of a substrate in the three regions. Areas in the guard ring that are not occupied by the diffusion regions are occupied by shallow trench isolation (STI) structures. Stripes of dummy structures may be formed over respective STI structures and may not overlap the diffusion regions. The diffusion regions in the first and third regions may be biased to a ground voltage. The diffusion regions in the second section may be biased to a positive power supply voltage.Type: GrantFiled: December 9, 2011Date of Patent: December 24, 2013Assignee: Altera CorporationInventors: Bradley Jensen, Charles Y. Chu
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Publication number: 20130140640Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.Type: ApplicationFiled: August 4, 2011Publication date: June 6, 2013Applicant: ALTERA CORPORATIONInventors: Dustin Do, Andy L. Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin
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Publication number: 20120261738Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.Type: ApplicationFiled: June 29, 2012Publication date: October 18, 2012Inventors: Dustin Do, Andy Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
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Patent number: 8217464Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.Type: GrantFiled: August 6, 2010Date of Patent: July 10, 2012Assignee: Altera CorporationInventors: Dustin Do, Andy L. Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
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Patent number: 8159044Abstract: An integrated circuit is provided with a spiral inductor and a transition zone surrounding the spiral inductor. The transition zone may have a geometry that is substantially eight-sided or octagonal. Metal layers in the transition zone may have metal fill that is substantially octagonal and arranged in rows and columns. If desired, square or rectangular metal fill be tiled with the substantially octagonal metal fill. Metal layers may also contain halved or quartered octagonal metal fill. Substrate in the transition zone may have octagonal substrate regions separated by shallow trench isolation regions. A polysilicon layer above the substrate may have square regions of polysilicon fill directly above the shallow trench regions in the substrate. Such arrangements may provide more uniform densities in transition zones with certain geometries.Type: GrantFiled: November 20, 2009Date of Patent: April 17, 2012Assignee: Altera CorporationInventors: Shuxian Chen, Fangyun Richter, Bradley Jensen, Yowjuang (Bill) Liu
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Publication number: 20120083094Abstract: Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may include first, second, and third regions. The first and third regions may include p-wells. The second region may include an n-well. Stripes of diffusion regions may be formed at the surface of a substrate in the three regions. Areas in the guard ring that are not occupied by the diffusion regions are occupied by shallow trench isolation (STI) structures. Stripes of dummy structures may be formed over respective STI structures and may not overlap the diffusion regions. The diffusion regions in the first and third regions may be biased to a ground voltage. The diffusion regions in the second section may be biased to a positive power supply voltage.Type: ApplicationFiled: December 9, 2011Publication date: April 5, 2012Inventors: Bradley Jensen, Charles Y. Chu
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Publication number: 20120032276Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.Type: ApplicationFiled: August 6, 2010Publication date: February 9, 2012Applicant: Altera CorporationInventors: Dustin Do, Andy Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
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Patent number: 8097925Abstract: Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may include first, second, and third regions. The first and third regions may include p-wells. The second region may include an n-well. Stripes of diffusion regions may be formed at the surface of a substrate in the three regions. Areas in the guard ring that are not occupied by the diffusion regions are occupied by shallow trench isolation (STI) structures. Stripes of dummy structures may be formed over respective STI structures and may not overlap the diffusion regions. The diffusion regions in the first and third regions may be biased to a ground voltage. The diffusion regions in the second section may be biased to a positive power supply voltage.Type: GrantFiled: March 26, 2010Date of Patent: January 17, 2012Assignee: Altera CorporationInventors: Bradley Jensen, Charles Y. Chu
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Publication number: 20110233717Abstract: Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may include first, second, and third regions. The first and third regions may include p-wells. The second region may include an n-well. Stripes of diffusion regions may be formed at the surface of a substrate in the three regions. Areas in the guard ring that are not occupied by the diffusion regions are occupied by shallow trench isolation (STI) structures. Stripes of dummy structures may be formed over respective STI structures and may not overlap the diffusion regions. The diffusion regions in the first and third regions may be biased to a ground voltage. The diffusion regions in the second section may be biased to a positive power supply voltage.Type: ApplicationFiled: March 26, 2010Publication date: September 29, 2011Inventors: Bradley Jensen, Charles Y. Chu
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Patent number: 7902611Abstract: An integrated circuit is provided with transistor body regions that may be independently biased. Some of the bodies may be forward body biased to lower threshold voltages and increase transistor switching speed. Some of the bodies may be reverse body biased to increase threshold voltages and decrease leakage current. The integrated circuit may be formed on a silicon substrate. Body bias isolation structures may be formed in the silicon substrate to isolate the bodies from each other. Body bias isolation structures may be formed from shallow trench isolation trenches. Doped regions may be formed at the bottom of the trenches using ion implantation. Oxide may be used to fill the trenches above the doped region. A deep well may be formed under the body regions. The deep well may contact the doped regions that are formed at the bottom of the trenches.Type: GrantFiled: November 27, 2007Date of Patent: March 8, 2011Assignee: Altera CorporationInventors: Irfan Rahim, Bradley Jensen, Peter J. McElheny
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Publication number: 20100090308Abstract: Metal-oxide-metal capacitors with bar vias are provided for integrated circuits. The capacitors may be formed in the interconnect layers of integrated circuits. Stacked bar vias and metal lines in the interconnect layers may be connected to form conductive vertical plates that span multiple interconnect layers. The capacitors with bar vias may be formed by placing multiple vertical plates formed from stacked bar vias and metal lines parallel to each other, alternating the polarity of adjacent vertical parallel plates to form multiple parallel plate capacitors. The parallel plates may be interconnected to form first and second terminals in a capacitor.Type: ApplicationFiled: October 10, 2008Publication date: April 15, 2010Inventors: Charu Sardana, Albert Ratnakumar, Bradley Jensen, Jeffrey T. Watt
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Publication number: 20090302421Abstract: A deep trench capacitor includes a trench having walls and a floor. The deep trench capacitor also includes a layer of gate oxide on the walls and floor. Gate polysilicon is deposited over the gate oxide.Type: ApplicationFiled: June 9, 2008Publication date: December 10, 2009Inventors: Charu Sardana, Bradley Jensen, Irfan Rahim, Jeffrey T. Watt
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Publication number: 20080091920Abstract: A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status.Type: ApplicationFiled: October 31, 2007Publication date: April 17, 2008Inventors: George Shaw, Martin McClurg, Bradley Jensen, Russell Fish, Charles Moore
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Publication number: 20080077911Abstract: A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status.Type: ApplicationFiled: October 31, 2007Publication date: March 27, 2008Inventors: George Shaw, Martin McClurg, Bradley Jensen, Russell Fish, Charles Moore