Patents by Inventor Bradley K. Fross

Bradley K. Fross has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10627444
    Abstract: An integrated circuit having an integrated logic analyzer can include a match circuit including at least one match cell, wherein each match cell is programmable at runtime to detect a signal state from a plurality of signal states for a probed signal. The integrated circuit can include a combine circuit configured to generate a first match signal indicating an occurrence of a first trigger condition based upon the detected signal state of each match cell, a capture and control circuit configured to determining addressing for storing trace data corresponding to the probed signal, and a trace storage memory configured to the store trace data at addresses determined by the capture and control circuit.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: April 21, 2020
    Assignee: XILINX, INC.
    Inventors: Michael E. Peattie, Bradley K. Fross
  • Patent number: 10445219
    Abstract: Extracting transaction level information from an interface can include tracking transactions of an interface within an integrated circuit (IC) using a plurality of counters within the IC, wherein the counters generate counter data corresponding to the transactions. The method can include capturing signals of the interface as trace data for a trace window using an integrated logic analyzer within the IC, wherein a start of the trace window begins after a start of the tracking of the transactions using the plurality of counters. The method can also include using a host data processing system coupled to the IC, determining transaction level information for the interface using the counter data and the trace data for the trace window.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: October 15, 2019
    Assignee: XILINX, INC.
    Inventors: Niloy Roy, Jake Chang, Bradley K. Fross
  • Patent number: 10161999
    Abstract: Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: December 25, 2018
    Assignee: XILINX, INC.
    Inventors: Heera Nand, Niloy Roy, Mahesh Sankroj, Siddharth Rele, Riyas Noorudeen Remla, Rajesh Bansal, Bradley K. Fross
  • Patent number: 9846449
    Abstract: An integrated circuit including a universal monitor system includes a detector circuit. The detector circuit includes a start trigger circuit receiving first signals, an end trigger circuit receiving second signals, and a latency circuit coupled to outputs of the start and end trigger circuits. The start trigger circuit detects a start event from the first signals. The end trigger circuit detects an end event from the second signals. The detector circuit further includes: a data trigger circuit receiving third signals and detecting transferred data therefrom; a first counter circuit coupled to the latency circuit and calculating a total latency; a second counter circuit coupled to at least one of the start trigger circuit and counting start events, or the end trigger circuit and counting end events; and a third counter circuit coupled to an output of the data trigger circuit and counting a total amount of data transferred.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: December 19, 2017
    Assignee: XILINX, INC.
    Inventors: Paul R. Schumacher, Graham F. Schelle, Bradley K. Fross
  • Patent number: 8224638
    Abstract: A method of managing programmable device configuration can include running a server configuration image within the programmable device and storing a different configuration image within a non-volatile memory communicatively linked with the programmable device. Responsive to a switch request sent from the client to the programmable device over the communications link, the different configuration image can be loaded into the programmable device.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: July 17, 2012
    Assignee: Xilinx, Inc.
    Inventors: Nabeel Shirazi, Chi Bun Chan, Bradley K. Fross, Shay Ping Seng, Jonathan B. Ballagh
  • Patent number: 7184946
    Abstract: Method and apparatus for interfacing a high-level modeling system (HLMS) with a reconfigurable hardware platform for co-simulation. In one embodiment a boundary-scan interface is coupled to the HLMS and is configured to translate HLMS-issued commands to signals generally compliant with a boundary-scan protocol, and translate signals generally compliant with a boundary-scan protocol to data compatible with the HLMS. A translator and a wrapper are implemented for configuration of the hardware platform. The translator translates between signals that generally compliant with the boundary-scan protocol and signals that are compliant with a second protocol. A component to be co-simulated is instantiated within the wrapper, and the wrapper transfers signals between the translator and the component.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: February 27, 2007
    Assignee: Xilinx, Inc.
    Inventors: Jonathan B. Ballagh, Nabeel Shirazi, Christopher N. Battson, Michael E. Darnall, Bradley K. Fross
  • Patent number: 7102555
    Abstract: Method and apparatus are described for providing analog capability with boundary-scanning for an integrated circuit. The integrated circuit includes a boundary-scan controller (1517) coupled to an analog-to-digital converter (200). An analog channel is selected for input to the analog-to-digital converter (200). Analog information is converted to digital information by the analog-to-digital converter (200), and then such digital information may be stored in data registers (209) for reading out via the boundary-scan controller (1517).
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: September 5, 2006
    Assignee: Xilinx, Inc.
    Inventors: Anthony J. Collins, David P. Schultz, Neil G. Jacobson, Edward S. McGettigan, Bradley K. Fross
  • Patent number: 7085706
    Abstract: Systems and methods utilizing virtual input/output (VIO) modules in PLDS. One or more VIO modules are embedded in a PLD along with the user circuit to be controlled and monitored. The VIO module includes a control module that acts as a virtual input module for the user circuit, and can optionally include a status module that acts as a virtual output module for the user circuit. A bi-directional data interface is provided between the user circuit and the VIO modules, and between the VIO modules and a communication module. The communication module is coupled through input/output pads of the PLD to an external communication link, and hence to a host computer in which resides software that controls the communication link. Thus, by interfacing with the host computer, a user can control the user circuit via the control modules and monitor output signals from the user circuit via the status modules.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: August 1, 2006
    Assignee: Xilinx, Inc.
    Inventors: Edward S. McGettigan, Bradley K. Fross, Michael E. Peattie
  • Publication number: 20040260528
    Abstract: Method and apparatus for interfacing a high-level modeling system (HLMS) with a reconfigurable hardware platform for co-simulation. In one embodiment a boundary-scan interface is coupled to the HLMS and is configured to translate HLMS-issued commands to signals generally compliant with a boundary-scan protocol, and translate signals generally compliant with a boundary-scan protocol to data compatible with the HLMS. A translator and a wrapper are implemented for configuration of the hardware platform. The translator translates between signals that generally compliant with the boundary-scan protocol and signals that are compliant with a second protocol. A component to be co-simulated is instantiated within the wrapper, and the wrapper transfers signals between the translator and the component.
    Type: Application
    Filed: June 19, 2003
    Publication date: December 23, 2004
    Applicant: Xilinx, Inc.
    Inventors: Jonathan B. Ballagh, Nabeel Shirazi, Christopher N. Battson, Michael E. Darnall, Bradley K. Fross
  • Patent number: 6384627
    Abstract: A method of configuring an FPGA lookup table to implement both exact and relative matching comparators is disclosed. Examples of exact matching of two variables, exact matching of a variable to a constant, relative matching (greater than) of a variable to a constant, and combined exact and relative matching are discussed. Use of the comparator to trigger a logic analyzer to collect data is discussed.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: May 7, 2002
    Assignee: Xilinx, Inc.
    Inventors: Bradley K. Fross, Edward S. McGettigan