Abstract: Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

Abstract: Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

Abstract: Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

Abstract: Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

Abstract: The invention, in its various aspects and embodiments, is a method and apparatus for controlling the operation of a multi-chamber process tool in a semiconductor fabrication process. The method comprises setting a plurality of operation parameters for the conduct of a predetermined operation in each of a plurality of process chambers in a multi-chamber process tool; performing the predetermined operation in each of the process chambers; examining a physical characteristic of a processed wafer from each of the process chambers; determining from the examined physical characteristics whether the operating conditions in each of the process chambers match; and resetting at least one operating parameter so that the operating conditions in each of the process chambers will match. The apparatus comprises a processing tool, a review station, and a tool controller. The processing tool includes a plurality of process chambers and an operation controller.

Abstract: A method for reducing deposition thickness variation in a processing tool comprises storing a post-clean performance model of the processing tool; receiving at least one of a showerhead age and a tool idle time associated with the processing tool as an input parameter; determining temperature control parameters based on the input parameter and the post-clean performance model; and modifying an operating recipe of the processing tool based on the temperature control parameters. A processing system includes a processing tool and an automatic process controller. The processing tool is adapted to process wafers in accordance with an operating recipe.

Abstract: A processing line includes a processing tool, a measurement tool, and an automatic process controller. The processing tool is adapted to process articles. The measurement tool is adapted to measure a characteristic of selected articles at a measurement frequency. The automatic process controller is adapted to change the measurement frequency based on a usage characteristic of the processing tool. A method for monitoring a processing tool includes processing a plurality of articles in the processing tool; measuring a characteristic of selected articles at a measurement frequency; and changing the measurement frequency based on a usage characteristic of the processing tool.

Abstract: A method is provided for determining the temperature of a semiconductor fabrication process in which a resistivity versus temperature calibration curve for a superlattice structure is created. A plurality of similar superlattice structures which include alternating layers of a conductor and a semiconductor may be annealed at different temperatures. The resistivity of each superlattice structure may then be measured after the superlattice structures have been cooled to room temperature in order to form the calibration curve. A similar superlattice structure may then be subjected to the temperature at which the semiconductor fabrication process is typically performed, causing the resistivity of the superlattice structure to change. Based on the resulting resistivity of the superlattice structure, the calibration curve may be used to determine the process temperature of the superlattice structure during the fabrication process.

Abstract: A method is provided for determining the temperature of a semiconductor fabrication process in which a resistivity versus temperature calibration curve for a superlattice structure is created. A plurality of similar superlattice structures which include alternating layers of a conductor and a semiconductor may be annealed at different temperatures. The resistivity of each superlattice structure may then be measured after the superlattice structures have been cooled to room temperature in order to form the calibration curve. A similar superlattice structure may then be subjected to the temperature at which the semiconductor fabrication process is typically performed, causing the resistivity of the superlattice structure to change. Based on the resulting resistivity of the superlattice structure, the calibration curve may be used to determine the process temperature of the superlattice structure during the fabrication process.