Abstract: A self-aligned magnetic clad bit line structure (274) for a magnetic memory element (240a) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure (274) extends within a trench (258) and includes a conductive material (264), magnetic cladding sidewalls (262) and a magnetic cladding cap (252). The magnetic cladding sidewalls (262) at least partially surround the conductive material (264) and the magnetic cladding cap (252) is substantially recessed within the trench with respect to the top of the trench.

Abstract: A self-aligned magnetic clad bit line structure (274) for a magnetic memory element (240a) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure (274) extends within a trench (258) and includes a conductive material (264), magnetic cladding sidewalls (262) and a magnetic cladding cap (252). The magnetic cladding sidewalls (262) at least partially surround the conductive material (264) and the magnetic cladding cap (252) is substantially recessed within the trench with respect to the top of the trench.

Abstract: A self-aligned magnetic clad bit line structure (274) for a magnetic memory element (240a) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure (274) extends within a trench (258) and includes a conductive material (250), magnetic cladding sidewalls (262) and a magnetic cladding cap (252). The magnetic cladding sidewalls (262) at least partially surround the conductive material (264) and the magnetic cladding cap (252) is substantially recessed within the trench with respect to the top of the trench.

Abstract: A dielectric film (110) is formed overlying a semiconductor device substrate (10). A dielectric post (204) having an outer peripheral boundary having sidewalls is formed over the dielectric film (110). A first conductive film (402) is deposited at least along the sidewalls of the dielectric post (204) to form a lower electrode. A capacitor dielectric film (1801) is deposited on the first conductive film, and a upper electrode (1802) is formed on the capacitor dielectric film (1801).

Abstract: A first etch stop layer (14) is formed over a semiconductor substrate (10). A first dielectric layer (20) is formed over the first etch stop layer (14). An opening (22) is formed in the first dielectric layer (20). The opening (22) extends through the first dielectric layer (20) and exposes a first conductive material (18) under the first dielectric layer (20). A second conductive material (30) is deposited over the semiconductor substrate (10) and within the opening (22). The second conductive material (30) electrically contacts the first conductive material (18). Portions of the second conductive material (30) lying outside of the opening (22) are removed and then portions of the first dielectric layer (20) are removed to expose portions of the first etch stop layer (14).

Abstract: A rapid thermal processing susceptor including a base having a planar surface and an upright sidewall extending around a periphery thereof and encircling a working portion of the planar surface. The working portion and the sidewall define a cavity. A plurality of minimum contact points extend from the working portion into the cavity and are positioned to receive thereon a semiconductor wafer. A cover is receivable by the sidewall for enclosing the cavity.

Abstract: A dielectric film (110) is formed overlying a semiconductor device substrate (10). A dielectric post (204) having an outer peripheral boundary having sidewalls is formed over the dielectric film (110). A first conductive film (402) is deposited at least along the sidewalls of the dielectric post (204) to form a lower electrode. A capacitor dielectric film (1801) is deposited on the first conductive film, and a upper electrode (1802) is formed on the capacitor dielectric film (1801).

Abstract: The present invention is a process for forming a lower capacitor electrode. Specifically, an oxygen tolerant bottom electrode layer (312) is formed over a conductive plug (216). A dielectric layer (420) is deposited and partially removed in order to form an inlaid bottom electrode structure. A capacitor dielectric (810) such as BST is formed over the lower electrode (310). The upper electrode (812) is formed over the capacitor dielectric (810) and the resulting stack is patterned in order to form a final capacitive device (916). In another embodiment of the present invention, a hardmask is formed over the bottom electrode (310) and removed prior to the capacitor dielectric (810) being formed.

Abstract: Metal doping agents are introduced into metal polyoxyalkylated liquid precursor solutions for use in processes for forming thin-layer capacitors (10) to be used in integrated circuits such as DRAMS and the like. The dopants serve to reduce capacitor leakage current by altering a dominant type of electron emission, as determined by a change in the slope of a line plotted as leakage current versus bias voltage. The specially doped precursor solutions preferably include mixtures of Ce, Cr, Dy, Mn, and Ti moieties.