Patents by Inventor Bradley N. Engel
Bradley N. Engel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6956764Abstract: A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device (12) having two bits (18) and (20) sandwiched between a word line (14) and a digit line (16) so that current waveforms (104) and (106) can be applied to the word and digit lines at various times to cause a magnetic field flux HW and HD to rotate the effective magnetic moment vectors (86) and (94) of the device (12) by approximately 180°. Each bit includes N ferromagnetic layers (32) and (34, 42) and (44, 60) and (62, 72 and 74) that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the bit. One or both bits may be programmed by adjusting the current in the word and/or digit lines.Type: GrantFiled: August 25, 2003Date of Patent: October 18, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Bradley N. Engel, Eric J. Salter, Jon M. Slaughter
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Patent number: 6927072Abstract: A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.Type: GrantFiled: March 8, 2002Date of Patent: August 9, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Jaynal A. Molla, John D'Urso, Kelly Kyler, Bradley N. Engel, Gregory W. Grynkewich, Nicholas D. Rizzo
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Patent number: 6909631Abstract: An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.Type: GrantFiled: October 2, 2003Date of Patent: June 21, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Mark A. Durlam, Thomas W. Andre, Mark F. DeHerrera, Bradley N. Engel, Bradley J. Garni, Joseph J. Nahas, Nicholas D. Rizzo, Saied Tehrani
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Patent number: 6898112Abstract: A nearly balanced synthetic antiferromagnetic (SAF) structure that can be advantageously used in magnetoelectronic devices such as a magnetoresistive memory cell includes two ferromagnetic layers and an antiferromagnetic coupling layer separating the two ferromagnetic layers. The SAF free layer has weakly coupled regions formed in the antiferromagnetic coupling layer by a treatment such as annealing, layering of the antiferromagnetic coupling layer, or forming the antiferromagnetic coupling layer over a roughened surface of a ferromagnetic layer. The weakly coupled regions lower the flop field of the SAF free layer in comparison to untreated SAF free layers. The SAF flop is used during the write operation of such a structure and its reduction results in lower power consumption during write operations and correspondingly increased device performance.Type: GrantFiled: December 18, 2002Date of Patent: May 24, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Jason Allen Janesky, Bradley N. Engel, Nicholas D. Rizzo, Jon M. Slaughter
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Patent number: 6888743Abstract: An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.Type: GrantFiled: December 27, 2002Date of Patent: May 3, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Mark A. Durlam, Thomas W. Andre, Brian R. Butcher, Mark F. Deherrera, Bradley N. Engel, Bradley J. Garni, Gregory W. Grynkewich, Joseph J. Nahas, Nicholas D. Rizzo, Saied Tehrani, Clarance J. Tracy
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Publication number: 20040264238Abstract: A direct write is provided for a magnetoelectronics information device that includes producing a first magnetic field with a first field magnitude in proximity to the magnetoelectronics information device at a first time (t1). Once this first magnetic field with the first magnitude is produced, a second magnetic field with a second field magnitude is produced in proximity to the magnetoelectronics information device at a second time (t2). The first magnetic field is adjusted to provide a third magnitude at a third time (t3) that is less than the first field magnitude and greater than zero, and the second magnetic field is adjusted to provide a fourth field magnitude at a fourth time (t4) that is less than the second field magnitude. This direct write is used in conjunction with other direct writes and also in combination with toggle writes to write the MRAM element without an initial read.Type: ApplicationFiled: June 27, 2003Publication date: December 30, 2004Inventors: Bengt J. Akerman, Mark F. Deherrera, Bradley N. Engel, Nicholas D. Rizzo
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Patent number: 6818961Abstract: A method of fabricating a magnetoresistive tunneling junction cell comprising the steps of providing a substrate with a surface, depositing a first magnetic region (17) having a resultant magnetic moment vector onto the substrate, depositing an electrically insulating material (16) onto the first magnetic region, and depositing a second magnetic region (15) onto the electrically insulating material, wherein at least a portion of one of the first and second magnetic regions is formed by depositing said region at a nonzero deposition angle relative to a direction perpendicular to the surface of the substrate to create an induced anisotropy.Type: GrantFiled: June 30, 2003Date of Patent: November 16, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Nicholas D. Rizzo, Bradley N. Engel, Jason A. Janesky, Jon M. Slaughter, Jijun Sun
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Patent number: 6760266Abstract: A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.Type: GrantFiled: June 28, 2002Date of Patent: July 6, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Bradley J. Garni, Mark F. Deherrera, Mark A. Durlam, Bradley N. Engel, Thomas W. Andre, Joseph J. Nahas, Chitra K. Subramanian
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Publication number: 20040125649Abstract: An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.Type: ApplicationFiled: October 2, 2003Publication date: July 1, 2004Inventors: Mark A. Durlam, Thomas W. Andre, Mark F. Deherrera, Bradley N. Engel, Bradley J. Garni, Joseph J. Nahas, Nicholas D. Rizzo, Saied Tehrani
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Publication number: 20040125646Abstract: An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.Type: ApplicationFiled: December 27, 2002Publication date: July 1, 2004Inventors: Mark A. Durlam, Thomas W. Andre, Brian R. Butcher, Mark F. Deherrera, Bradley N. Engel, Bradley J. Garni, Gregory W. Grynkewich, Joseph J. Nahas, Nicholas D. Rizzo, Saied Tehrani, Clarance J. Tracy
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Publication number: 20040120184Abstract: A nearly balanced synthetic antiferromagnetic (SAF) structure that can be advantageously used in magnetoelectronic devices such as a magnetoresistive memory cell includes two ferromagnetic layers and an antiferromagnetic coupling layer separating the two ferromagnetic layers. The SAF free layer has weakly coupled regions formed in the antiferromagnetic coupling layer by a treatment such as annealing, layering of the antiferromagnetic coupling layer, or forming the antiferromagnetic coupling layer over a roughened surface of a ferromagnetic layer. The weakly coupled regions lower the flop field of the SAF free layer in comparison to untreated SAF free layers. The SAF flop is used during the write operation of such a structure and its reduction results in lower power consumption during write operations and correspondingly increased device performance.Type: ApplicationFiled: December 18, 2002Publication date: June 24, 2004Inventors: Jason Allen Janesky, Bradley N. Engel, Nicholas D. Rizzo, Jon M. Slaughter
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Patent number: 6720597Abstract: A cladded conductive interconnect for programming a magnetoresistive memory device which includes a conductive material with a length, a first barrier conductive material positioned on the conductive material, and a multi-layer cladding region positioned along the length of the conductive material wherein the multi-layer cladding region includes N ferromagnetic layers, where N is a whole number greater than or equal to two, and wherein the multi-layer cladding region further includes at least one spacer layer, wherein the spacer layer can include a metal, an insulator, or an exchange interaction material, and wherein the spacer layer is sandwiched therebetween each adjacent ferromagnetic layer.Type: GrantFiled: November 13, 2001Date of Patent: April 13, 2004Assignee: Motorola, Inc.Inventors: Jason Allen Janesky, Nicholas D. Rizzo, Bradley N. Engel
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Patent number: 6714446Abstract: A magnetoelectronics information device is provided that includes two multi-layer structures and a spacer layer interposed between the two multi-layer structures. Each of the multi-layer structures has two magnetic sublayers and a spacer layer interposed between the two magnetic sublayers. The spacer layer interposed between the two magnetic sublayers provides an antiferromagnetic exchange coupling that is quantified by a saturation field. The spacer layer interposed between the two multi-layer structures provides a second antiferromagnetic exchange coupling is quantified by another saturation field that is less than the first saturation field.Type: GrantFiled: May 13, 2003Date of Patent: March 30, 2004Assignee: Motorola, Inc.Inventor: Bradley N. Engel
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Publication number: 20040023365Abstract: The preferred embodiments of the present invention use MRAM technology to detect a shift in the magnetic switching field of a sensor. The shift in the magnetic switching field is caused by the presence of magnetic tagged beads. By measuring the magnitude of the shift in the magnetic field and correlating the magnitude of the shift to the presence of the target molecules, accurate measurements regarding the presence of the target molecules can be made.Type: ApplicationFiled: July 31, 2002Publication date: February 5, 2004Inventors: Bradley N. Engel, Michael Ward
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Patent number: 6674618Abstract: A dual active element magnetoresistive tape read head uses weak biasing of active layers to reduce Barkhausen noise. The read head includes a first insulator layer. A first active magnetoresistive layer is built on the first insulator layer. A second insulator layer is built on the first active magnetoresistive layer. A second active magnetoresistive layer is on the second insulator layer. The second active magnetoresistive layer is magnetostatically coupled to the first active magnetoresistive layer. A third insulator layer is on the second active magnetoresistive layer. At least one insulator layer is a biasing layer comprised of an electrically nonconductive antiferromagnetic material.Type: GrantFiled: June 22, 2001Date of Patent: January 6, 2004Assignee: Storage Technology CorporationInventors: Bradley N. Engel, Richard H. Dee, Robert B. Chesnutt
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Publication number: 20040001383Abstract: A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Inventors: Bradley J. Garni, Mark F. Deherrera, Mark A. Durlam, Bradley N. Engel, Thomas W. Andre, Joseph J. Nahas, Chitra K. Subramanian
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Patent number: 6654278Abstract: A magnetoresistive tunneling junction memory cell comprises a magnetoresistive tunneling barrier (16), a bit magnetic region (15), a reference magnetic region (17), and current lines (20, 30) for inducing an applied magnetic field in the bit and reference magnetic regions. The bit magnetic region has a bit magnetic moment (43, 40,1425, 1625, 1950, 2315) that has a polarity in a bit easy axis (59, 1435) when there is no applied magnetic field. The tunneling barrier and the bit and reference magnetic regions form a magnetoresistive tunneling junction device (10, 72, 73, 74, 75, 76). In some implementations (73, 74, 75), the reference magnetic region has a reference magnetic moment (40, 1430, 1440, 1920, 1925) that is non-parallel to the bit easy axis. In other implementations (76), the reference magnetic region has a magnetization vortex (2310) with a net reference magnetic moment that is essentially zero.Type: GrantFiled: July 31, 2002Date of Patent: November 25, 2003Assignee: Motorola, Inc.Inventors: Bradley N. Engel, Jason Allen Janesky
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Patent number: 6633498Abstract: A magnetoresistive tunneling junction memory cell (10) including a pinned ferromagnetic region (17) having a magnetic moment vector (47) fixed in a preferred direction in the absence of an applied magnetic field wherein the pinned ferromagnetic region has a magnetic fringing field (96), an electrically insulating material positioned on the pinned ferromagnetic region to form a magnetoresistive tunneling junction (16), and a free ferromagnetic region (15) having a magnetic moment vector (53) oriented in a position parallel or anti-parallel to that of the pinned ferromagnetic region wherein the magnetic fringing field is chosen to obtain a desired switching field.Type: GrantFiled: June 18, 2002Date of Patent: October 14, 2003Assignee: Motorola, Inc.Inventors: Bradley N. Engel, Jason Allen Janesky, Nicholas D. Rizzo
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Publication number: 20030170976Abstract: A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.Type: ApplicationFiled: March 8, 2002Publication date: September 11, 2003Inventors: Jaynal A. Molla, John D'Urso, Kelly Kyler, Bradley N. Engel, Gregory W. Grynkewich, Nicholas D. Rizzo
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Publication number: 20030128603Abstract: A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device sandwiched between a word line and a digit line so that current waveforms can be applied to the word and digit lines at various times to cause a magnetic field flux to rotate the effective magnetic moment vector of the device by approximately 180°. The magnetoresistive memory device includes N ferromagnetic layers that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the device.Type: ApplicationFiled: January 9, 2003Publication date: July 10, 2003Inventors: Leonid Savtchenko, Anatoli A. Korkin, Bradley N. Engel, Nicholas D. Rizzo, Mark F. Deherrera, Jason Allen Janesky