Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

Abstract: A PV module is formed having an array of PV cells, where the cells are separated by gaps. Each cell contains an array of small silicon sphere diodes (10-300 microns in diameter) connected in parallel. The diodes and conductor layers may be patterned by printing. A continuous metal substrate supports the diodes and conductor layers in all the cells. A dielectric substrate is laminated to the metal substrate. Trenches are then formed by laser ablation around the cells to sever the metal substrate to form electrically isolated PV cells. A metallization step is then performed to connect the cells in series to increase the voltage output of the PV module. An electrically isolated bypass diode for each cell is also formed by the trenching step. The metallization step connects the bypass diode and its associated cell in a reverse-parallel relationship.

Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

Abstract: An initially flat light sheet is formed by printing conductor layers and microscopic LEDs over a flexible substrate to connect the LEDs in parallel. The light sheet is then subjected to a molding process which forms 3-dimensional features in the light sheet, such as bumps of any shape. The features may be designed to create a desired light emission profile, increase light extraction, and/or create graphical images. In one embodiment, an integrated light sheet and touch sensor is formed, where the molded features convey touch positions of the sensor. In one embodiment, a curable resin is applied to the light sheet to fix the molded features. In another embodiment, optical features are molded over the flat light sheet. In another embodiment, each molded portion of the light sheet forms a separate part that is then singulated from the light sheet.

Abstract: A method of forming a light sheet includes depositing a reflective conductor layer over a substrate, printing a layer of microscopic inorganic LEDs on the conductor layer, depositing a first dielectric layer, having a first index of refraction, over the conductor layer and along sidewalls of the LEDs, and depositing a transparent conductor layer over the LEDs so that the LEDs are connected in parallel. The transparent conductor layer may be a wire mesh with openings. A liquid or paste polymer layer is then deposited over the transparent conductor layer and directly contacts the first dielectric layer. The indices of refraction of both layers are similar to reduce TIR. The top surface of the polymer layer is then molded to contain light extraction features to reduce waveguiding in the light sheet. In another embodiment, the substrate surface is the light exit surface that has the light extraction features.

Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

Abstract: A PV module is formed having an array of PV cells, where the cells are separated by gaps. Each cell contains an array of small silicon sphere diodes (10-300 microns in diameter) connected in parallel. The diodes and conductor layers may be patterned by printing. A continuous metal substrate supports the diodes and conductor layers in all the cells. A dielectric substrate is laminated to the metal substrate. Trenches are then formed by laser ablation around the cells to sever the metal substrate to form electrically isolated PV cells. A metallization step is then performed to connect the cells in series to increase the voltage output of the PV module. An electrically isolated bypass diode for each cell is also formed by the trenching step. The metallization step connects the bypass diode and its associated cell in a reverse-parallel relationship.

Abstract: An LED module is disclosed containing an integrated driver transistor (e.g, a MOSFET) in series with an LED. In one embodiment, LED layers are grown over a substrate. The transistor regions are formed over the same substrate. After the LED layers, such as GaN layers, are grown to form the LED portion, a central area of the LED is etched away to expose a semiconductor surface in which the transistor regions are formed. A conductor connects the transistor in series with the LED. Another node of the transistor is electrically coupled to an electrode on the bottom surface of the substrate. In one embodiment, an anode of the LED is connected to one terminal of the module, one current carrying node of the transistor is connected to a second terminal of the module, and the control terminal of the transistor is connected to a third terminal of the module.

Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

Abstract: A PV module is formed having an array of PV cells, where the cells are separated by gaps. Each cell contains an array of small silicon sphere diodes (10-300 microns in diameter) connected in parallel. The diodes and conductor layers may be patterned by printing. A continuous metal substrate supports the diodes and conductor layers in all the cells. A dielectric substrate is laminated to the metal substrate. Trenches are then formed by laser ablation around the cells to sever the metal substrate to form electrically isolated PV cells. A metallization step is then performed to connect the cells in series to increase the voltage output of the PV module. An electrically isolated bypass diode for each cell is also formed by the trenching step. The metallization step connects the bypass diode and its associated cell in a reverse-parallel relationship.

Abstract: Relatively small, electrically isolated segments of LED light sheets are fabricated having an anode terminal and a cathode terminal. The segments contain microscopic printed LEDs that are connected in parallel by two conductive layers sandwiching the LEDs. The top conductive layer is transparent. Separately formed from the light sheet segments is a flexible, large area conductor backplane having a single layer or multiple layers of solid metal strips (traces). The segments are laminated over the backplane's metal pattern to supply power to the segment terminals. An adhesive layer secures the segments to the backplane. The metal pattern may connect the segments in series, or parallel, or form an addressable circuit for a display. The segments may be on a common substrate or physically separated from each other prior to the lamination.

Abstract: A first layer of inorganic first vertical LED dies (VLEDs) of a first color is printed on a conductor surface. A first transparent conductor layer is deposited over the first VLEDs to electrically contact top electrodes of the first VLEDs. An electrically insulated second layer of second VLEDs of a second color is printed over the first transparent conductor layer, and an electrically insulated third layer of third VLEDs of a third color is printed over the first transparent conductor layer. For a color display, the VLEDs are printed in an addressable pixel array. Since the VLEDs are printed as an ink, the overlying VLEDs in a pixel are not vertically aligned, so there is little blockage of light. If the structure is used for general illumination, the VLEDs do not need to be printed in pixel areas.

Abstract: In one embodiment, a vertical LED die is formed by epitaxially growing over a sapphire substrate a transparent first conductive oxide layer, followed by an n-type GaN-based layer, followed by a GaN-based active layer, followed by a p-type GaN-based layer, followed by a transparent second conductive oxide layer. The transparent conductive oxide has a Wurtzite crystal structure that enables epitaxially growth of GaN-based layers over the conductive oxide. The substrate is then removed. The two conductive oxide layers may be top and bottom electrodes for the LED die. Since all layers are epitaxially grown, fabrication is simplified. The LED dies may be microscopic and printed as an ink over a bottom conductive layer that electrically contacts one of the transparent conductive oxide layers. The LED dies are sandwiched between the bottom conductive layer and a top conductive layer to form an ultra-thin flexible light sheet.

Abstract: In one example of forming a printable vertical LED that can emit light from its top and bottom surfaces, a transparent insulating material, such as silicon nitride, is formed over the bottom semiconductor layers of the LED. The insulating material is then patterned to expose portions of the conductive semiconductor layer or a transparent current spreading layer. The shape and thickness of the patterned insulating material over the bottom surface can be selected to achieve a desired orientation of the printed LED and the desired spreading of current. A thin layer of a transparent conductive material is then deposited over the surfaces of the insulating material and the exposed semiconductor surface, including the sidewalls of the openings. The top bump of the LED may be formed using the existing undoped GaN as the patterned insulating material, or an insulating layer may be deposited and patterned.

Abstract: In a method for forming a phosphor-converted LED, an array of vertical LEDs is printed over a conductive surface of a substrate such that a bottom electrode of the LEDs ohmically contacts the conductive surface. A dielectric layer then formed over the conductive surface. An electrically conductive phosphor layer is deposited over the dielectric layer and the LEDs to ohmically contact the top surface of the LEDs and connect the LEDs in parallel. The conductive phosphor layer is formed by phosphor particles intermixed with a transparent conductor material. One or more metal contacts over the conductive phosphor layer conduct current through the conductive phosphor layer and the LEDs to illuminate the LEDs. A portion of light generated by the LED leaks through the conductive phosphor layer, and the combination of the LED light and phosphor light creates a composite light.

Abstract: A method of forming a light sheet includes printing a layer of inorganic LEDs on a first conductive surface of a substrate, depositing a first dielectric layer, and depositing a second conductor layer over the LEDs so that the LEDs are connected in parallel. At least one of the first conductive surface or the second conductor layer is transparent to allow light to escape. A phosphor layer may be formed over the light sheet so that the LED light mixed with the phosphor light creates white light. The flat light sheet is then folded, such as by molding, to form a three-dimensional structure with angled light emitting walls and reflective surfaces to control a directionality of the emitted light and improve the mixing of light. The folds may form rows of angled walls or polygons.

Abstract: Relatively small, electrically isolated LED tiles or PV tiles are fabricated having an anode electrode and a cathode electrode. The LED tiles contain microscopic printed LEDs that are connected in parallel by two conductive layers sandwiching the LEDs. The top conductive layer is transparent. Separately formed from the tiles is a large area backplane having a single layer or multiple layers of metal traces connected to backplane electrodes corresponding to the tile electrodes. Multiple tiles are laminated over the backplane's metal pattern to connect the tile electrodes to the backplane electrodes, such as by a conductive adhesive. The backplane metal pattern may connect the tiles in series and/or parallel, or form an addressable circuit for a display. Groups of tiles may be physically connected to each other prior to the lamination to ease handling and alignment. The backplane has power terminals electrically coupled to the metal traces for receiving power.