Abstract: A system, method, and apparatus for inline audio/visual conversion are described. Power to an inline converter is provided over the A/V cable that couples the converter to a destination such as a selector.

Abstract: A system, method, and apparatus for inline audio/visual conversion are described. Power to an inline converter is provided over the A/V cable that couples the converter to a destination such as a selector.

Abstract: A system, method, and apparatus for inline audio/visual conversion are described. Power to an inline converter is provided over the A/V cable that couples the converter to a destination such as a selector.

Abstract: A monitor interface cable for transmitting display data and command data between a computer system and a display monitor preferably including a microcontroller. The monitor interface cable enables both display and command data to be transmitted simultaneously from the computer system to the display monitor.

Abstract: A monitor interface cable for transmitting display data and command data between a computer system and a display monitor preferably including a microcontroller. The monitor interface cable enables both display and command data to be transmitted simultaneously from the computer system to the display monitor. Inside the computer system, data containing the commands written to a particular memory location in a video buffer card is applied to various signal lines located in the monitor interface cable. These signal lines are coupled to the microcontroller located in the display monitor which receives the commands and performs various controlling functions in response. Status information in the form of a command is transmitted back across a second signal line to the computer system where various software programs including drivers receive and process the status information. Display data is simultaneously transmitted over other signal lines also located in the monitor interface cable.

Abstract: A memory controller method and apparatus wherein data to be written to a memory device is stored in a data queue, the data queue has a plurality of entries wherein at least two of the entries are combined to store a single datum, the single datum is wider than a single entry of the entries and addresses associated with the stored data of the data queue are stored in an address queue, thereby providing a circular write buffer. Specific memory modules of a plurality of memory modules to be refreshed are indicated to a refresh controller to thereby selectively control which of the memory modules are refreshed by the refresh controller. Access is controlled to the plurality of memory modules, each of the memory modules having an associated type. Configuration status information indicating the associated type for each of the memory modules is stored so that, if an access operation is performed to a wrong type, uncorrectable error faults are generated and can be detected.

Abstract: A method and apparatus is disclosed for interleaving the transfer of pixel data from a dual bank frame buffer to a memory display interface. The interleaved transfer of pixel data to the memory display interface enables upgrade of existing memory display interface designs to higher density VRAM chips in order to increase the capacity of the frame buffer.

Abstract: A method and apparatus is disclosed for interleaving the transfer of pixel data from a dual bank frame buffer to a memory display interface. The interleaved transfer of pixel data to the memory display interface enables upgrade of existing memory display interface designs to higher density VRAM chips in order to increase the capacity of the frame buffer.

Abstract: A method and apparatus for synchronizing pixel data flow within a memory display interface (MDI) to enable variable pixel depths, and to support display devices requiring differing pixel rates. A clock circuit receives a pixel clock from a DAC, and generates a shift clock (VSCLK), a pipeline clock, and an input control signal, all of which are synchronized to the pixel clock. The pixel clock synchronizes color pixel data transfer from the MDI to the DAC. The pipeline clock synchronizes pixel data processing through a pixel processing pipeline according to the frequency of the pixel clock and the number of pixels processed in parallel through the pixel processing pipeline. The input control signal feeds the pixel data from a VRAM frame buffer into the pixel processing pipeline according to the pixel depth mode, the frequency of the pixel clock, and the number of pixels processed in parallel through the pixel processing pipeline.

Abstract: A test mode read back function for verifying the functions of the memory display interface and a VRAM frame buffer coupled to the memory display interface, wherein the memory display interface implements programmable pixel rates and pixel depths, and programmable pixel processing functions.