Patents by Inventor Bradly George Frey
Bradly George Frey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240028772Abstract: A computer system, processor, and/or method for changing the mode of operation of a computer without rebooting includes: a processor having a configuration register, the configuration register having a privilege entry (PRVS) register field for each of one or more privilege levels, each PRVS register field for each privilege level having one or more control aspect entries; and an enforce below (ENFB) register field, each ENFB register field for each privilege level having one or more control aspect entries, the PRVS register field control aspects being equal in number to and corresponding to the ENRB register field control aspects. The PRVS register fields and the ENFB register fields are used to change the processor from a secure mode to a performance mode while running software applications.Type: ApplicationFiled: October 3, 2023Publication date: January 25, 2024Inventors: Debapriya Chatterjee, Christian Zoellin, Bradly George Frey, Brian W. Thompto
-
Patent number: 11797713Abstract: A computer system, processor, and/or method for changing the mode of operation of a computer without rebooting includes: a processor having a configuration register, the configuration register having a privilege entry (PRVS) register field for each of one or more privilege levels, each PRVS register field for each privilege level having one or more control aspect entries; and an enforce below (ENFB) register field, each ENFB register field for each privilege level having one or more control aspect entries, the PRVS register field control aspects being equal in number to and corresponding to the ENRB register field control aspects. The PRVS register fields and the ENFB register fields are used to change the processor from a secure mode to a performance mode while running software applications.Type: GrantFiled: December 16, 2020Date of Patent: October 24, 2023Assignee: International Business Machines CorporationInventors: Debapriya Chatterjee, Christian Zoellin, Bradly George Frey, Brian W. Thompto
-
Patent number: 11461474Abstract: The present disclosure relates to a process-based virtualization system comprising a data processing unit. The system comprises a computer readable storage media, wherein a first memory component of the computer readable storage media is configured for access by an OS, secure and non-secure applications and the firmware, and wherein a second memory component of the computer readable storage media is configured for access by the firmware and not by the OS and the non-secure application. The data processing unit is configured to operate in a first mode of operation that executes a non-secure application process using the OS, and to operate in a second mode of operation that executes the secure application using the firmware, thereby executing application code using the second memory component.Type: GrantFiled: January 24, 2020Date of Patent: October 4, 2022Assignee: International Business Machines CorporationInventors: Jentje Leenstra, Paul Mackerras, Benjamin Herrenschmidt, Bradly George Frey, John Martin Ludden, Guerney D. H. Hunt, David Campbell
-
Publication number: 20220188464Abstract: A computer system, processor, and/or method for changing the mode of operation of a computer without rebooting includes: a processor having a configuration register, the configuration register having a privilege entry (PRVS) register field for each of one or more privilege levels, each PRVS register field for each privilege level having one or more control aspect entries; and an enforce below (ENFB) register field, each ENFB register field for each privilege level having one or more control aspect entries, the PRVS register field control aspects being equal in number to and corresponding to the ENRB register field control aspects. The PRVS register fields and the ENFB register fields are used to change the processor from a secure mode to a performance mode while running software applications.Type: ApplicationFiled: December 16, 2020Publication date: June 16, 2022Inventors: Debapriya Chatterjee, Christian Zoellin, Bradly George Frey, Brian W. Thompto
-
Publication number: 20210232693Abstract: The present disclosure relates to a process-based virtualization system comprising a data processing unit. The system comprises a computer readable storage media, wherein a first memory component of the computer readable storage media is configured for access by an OS, secure and non-secure applications and the firmware, and wherein a second memory component of the computer readable storage media is configured for access by the firmware and not by the OS and the non-secure application. The data processing unit is configured to operate in a first mode of operation that executes a non-secure application process using the OS, and to operate in a second mode of operation that executes the secure application using the firmware, thereby executing application code using the second memory component.Type: ApplicationFiled: January 24, 2020Publication date: July 29, 2021Inventors: Jentje Leenstra, Paul Mackerras, Benjamin Herrenschmidt, Bradly George Frey, John Martin Ludden, Guerney D. H. Hunt, David Campbell
-
Patent number: 8645667Abstract: An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled.Type: GrantFiled: July 16, 2012Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Bradly George Frey, Michal Ostrowski, Andrew Henry Wottreng
-
Patent number: 8589657Abstract: An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled.Type: GrantFiled: January 4, 2011Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Bradly George Frey, Michal Ostrowski, Andrew Henry Wottreng
-
Publication number: 20120284465Abstract: An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled.Type: ApplicationFiled: July 16, 2012Publication date: November 8, 2012Applicant: International Business Machines CorporationInventors: Bradly George Frey, Michal Ostrowski, Andrew Henry Wottreng
-
Publication number: 20120173842Abstract: An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled.Type: ApplicationFiled: January 4, 2011Publication date: July 5, 2012Applicant: International Business Machines CorporationInventors: Bradly George Frey, Michal Ostrowski, Andrew Henry Wottreng
-
Patent number: 8140759Abstract: A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.Type: GrantFiled: April 16, 2009Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Bradly George Frey, Guy Lynn Guthrie, Cathy May, Ramakrishnan Rajamony, Balaram Sinharoy, William John Starke, Peter Kenneth Szwed
-
Patent number: 7904661Abstract: A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.Type: GrantFiled: December 10, 2007Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Eric Jason Fluhr, Bradly George Frey, John Barry Griswell, Jr., Hung Qui Le, Cathy May, Francis Patrick O'Connell, Edward John Silha, Albert Thomas Williams
-
Patent number: 7827343Abstract: The present invention provides a method and apparatus for processing a bus protocol packet in order to provide accelerator support. A component receives a bus protocol packet having a requester identifier. The component looks up an agent routing field. The component routes the bus protocol packet to an accelerator agent based on the agent routing field. It processes the bus protocol packet at the accelerator agent based on the agent routing field.Type: GrantFiled: September 20, 2007Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Bradly George Frey, Steven Mark Thurber, Andrew Henry Wottreng
-
Publication number: 20100268886Abstract: A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.Type: ApplicationFiled: April 16, 2009Publication date: October 21, 2010Applicant: INTERNATIONAL BUISNESS MACHINES CORPORATIONInventors: Bradly George Frey, Guy Lynn Guthrie, Cathy May, Ramakrishnan Rajamony, Balaram Sinharoy, William John Starke, Peter Kenneth Szwed
-
Publication number: 20090083471Abstract: The present invention provides a method and apparatus for processing a bus protocol packet in order to provide accelerator support. A component receives a bus protocol packet having a requester identifier. The component looks up an agent routing field. The component routes the bus protocol packet to an accelerator agent based on the agent routing field. It processes the bus protocol packet at the accelerator agent based on the agent routing field.Type: ApplicationFiled: September 20, 2007Publication date: March 26, 2009Inventors: Bradly George Frey, Steven Mark Thurber, Andrew Henry Wottreng
-
Publication number: 20080307190Abstract: A method for providing virtual real memory includes receiving a request for a memory page from a requestor. A system determines whether the requested memory page is available. In the event the requested memory page is available, the system satisfies the request. In the event the requested memory page is not available, the system generates a page fault interrupt, wherein the page fault interrupt comprises a first page fault correlation number (PFCID) identifying a restorative process, and wherein the restorative process is configured to restore the requested memory page to available memory. The system monitors a plurality of pending processes and determines whether the restorative process is complete. In the event the restorative process is complete, the system notifies the requester that the restorative process is complete.Type: ApplicationFiled: June 7, 2007Publication date: December 11, 2008Inventors: Richard Louis Arndt, Bradly George Frey
-
Patent number: 7350029Abstract: A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.Type: GrantFiled: February 10, 2005Date of Patent: March 25, 2008Assignee: International Business Machines CorporationInventors: Eric Jason Fluhr, Bradly George Frey, John Barry Griswell, Jr., Hung Qui Le, Cathy May, Francis Patrick O'Connell, Edward John Silha, Albert Thomas Williams
-
Patent number: 6338119Abstract: A method and apparatus for improving direct memory access and cache performance utilizing a special Input/Output or “I/O” page, defined as having a large size (e.g., 4 Kilobytes or 4 Kb), but with distinctive cache line characteristics. For Direct Memory Access (DMA) reads, the first cache line in the I/O page may be accessed, by a Peripheral Component Interconnect (PCI) Host Bridge, as a cacheable read and all other lines are non-cacheable access (DMA Read with no intent to cache). For DMA writes, the PCI Host Bridge accesses all cache lines as cacheable. The PCI Host Bridge maintains a cache snoop granularity of the I/O page size for data, which means that if the Host Bridge detects a store (invalidate) type system bus operation on any cache line within an I/O page, cached data within that page is invalidated, the Level 1 and Level 2 ((L1/L2) caches continue to treat all cache lines in this page as cacheable).Type: GrantFiled: March 31, 1999Date of Patent: January 8, 2002Assignee: International Business Machines CorporationInventors: Gary Dean Anderson, Ronald Xavier Arroyo, Bradly George Frey, Guy Lynn Guthrie
-
Patent number: 5835738Abstract: An information processing system comprises a processor, a first bus for conducting signals in accordance with a first bus protocol that does not support I/O address signals; a second bus for conducting signals in accordance with a second bus protocol that supports input/output (I/O) address signals; and a bridge circuit for coupling the first bus to the second bus. The processor includes a circuit for emitting address signals and an address type signal directed to a selected peripheral device. The bridge circuit comprises a filter for determining whether the address signal emitted by the processor corresponds to a peripheral device coupled to a bus subordinate to the bridge circuit; and a translation circuit, coupled to the filter, for translating signals in accordance with the first bus protocol to signals in accordance with the second bus protocol for transmission to the selected peripheral device.Type: GrantFiled: June 24, 1996Date of Patent: November 10, 1998Assignee: International Business Machines CorporationInventors: John Wiley Blackledge, Jr., Bechara Boury, Bradly George Frey, James D. Reid, Ronald Valli