Patents by Inventor Brain Hang Wai Yang

Brain Hang Wai Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Output queued switch with a parallel shared memory, and method of operating same
    Patent number: 7835334
    Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: November 16, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Kai-Yeung (Sunny) Siu, Brain Hang Wai Yang, Mizanur M. Rahman
  • OUTPUT QUEUED SWITCH WITH A PARALLEL SHARED MEMORY, AND METHOD OF OPERATING SAME
    Publication number: 20080310418
    Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.
    Type: Application
    Filed: August 26, 2008
    Publication date: December 18, 2008
    Inventors: Kai-Yeung (Sunny) Siu, Brain Hang Wai Yang, Mizanur M. Rahman
  • Network switch with a parallel shared memory
    Patent number: 7420969
    Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: September 2, 2008
    Assignee: RMI Corporation
    Inventors: Kai-Yeung (Sunny) Siu, Brain Hang Wai Yang, Mizanur M. Rahman
  • Programmable integrated circuit for use in a network switch
    Patent number: 7072345
    Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: July 4, 2006
    Assignee: Raza Microelectronics, Inc
    Inventors: Kai-Yeung (Sunny) Siu, Brain Hang Wai Yang, Mizanur M. Rahman
  • Network switch for routing network traffic
    Patent number: 7046681
    Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: May 16, 2006
    Assignee: Raza Microelectronics, Inc.
    Inventors: Kai-Yeung (Sunny) Siu, Brain Hang Wai Yang, Mizanur M. Rahman
  • Method of routing network traffic
    Publication number: 20020064130
    Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.
    Type: Application
    Filed: August 24, 2001
    Publication date: May 30, 2002
    Inventors: Kai-Yeung (Sunny) Siu, Brain Hang Wai Yang, Mizanur M. Rahman
  • Network switch with a parallel shared memory
    Publication number: 20020064170
    Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.
    Type: Application
    Filed: August 24, 2001
    Publication date: May 30, 2002
    Inventors: Kai-Yeung (Sunny) Siu, Brain Hang Wai Yang, Mizanur M. Rahman
  • Programmable integrated circuit for use in a network switch
    Publication number: 20020064172
    Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.
    Type: Application
    Filed: August 24, 2001
    Publication date: May 30, 2002
    Inventors: Kai-Yeung (Sunny) Siu, Brain Hang Wai Yang, Mizanur M. Rahman