Patents by Inventor Bram ROOSELEER
Bram ROOSELEER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11651816Abstract: There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.Type: GrantFiled: July 22, 2021Date of Patent: May 16, 2023Assignee: SURECORE LIMITEDInventors: Stefan Cosemans, Bram Rooseleer
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Publication number: 20210350841Abstract: There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.Type: ApplicationFiled: July 22, 2021Publication date: November 11, 2021Inventors: Stefan COSEMANS, Bram ROOSELEER
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Patent number: 11100978Abstract: There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.Type: GrantFiled: June 2, 2017Date of Patent: August 24, 2021Assignee: Surecore LimitedInventors: Stefan Cosemans, Bram Rooseleer
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Patent number: 10867666Abstract: There is provided a memory unit comprising an array of memory cells and a driver circuit configured to output an output address signal that addresses a portion/subset of the array of memory cells. The driver circuit comprises a logic gate that is configured to receive one or more input address signals and to provide an output address signal in dependence upon the one or more input address signals, and wherein the logic gate is configured to output a drive voltage provided by a first of the one or more input address signals as the output address signal when the output of the logic gate is true/high.Type: GrantFiled: June 2, 2017Date of Patent: December 15, 2020Assignee: SURECORE LIMITEDInventors: Stefan Cosemans, Bram Rooseleer
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Publication number: 20200327931Abstract: There is provided a memory unit comprising an array of memory cells and a driver circuit configured to output an output address signal that addresses a portion/subset of the array of memory cells. The driver circuit comprises a logic gate that is configured to receive one or more input address signals and to provide an output address signal in dependence upon the one or more input address signals, and wherein the logic gate is configured to output a drive voltage provided by a first of the one or more input address signals as the output address signal when the output of the logic gate is true/high.Type: ApplicationFiled: June 2, 2017Publication date: October 15, 2020Inventors: Stefan COSEMANS, Bram ROOSELEER
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Publication number: 20200327924Abstract: There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.Type: ApplicationFiled: June 2, 2017Publication date: October 15, 2020Inventors: Stefan COSEMANS, Bram ROOSELEER
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Patent number: 10593395Abstract: There is provided a multiple data rate memory configured to implement first and second memory accesses within a single cycle of an external clock signal. The memory comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to at least one local bit line, the at least one local bit line of each memory cell group being connected to a local-to-global interface circuit. The local-to-global interface circuit is configured to control the state of at least one first global bit line in dependence upon the state of the at least one local bit line during the first memory access and to control the state of at least one second global bitline in dependence upon the state of the at least one local bit line during the second memory access.Type: GrantFiled: February 28, 2017Date of Patent: March 17, 2020Assignee: SURECORE LIMITEDInventors: Stefan Cosemans, Bram Rooseleer
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Publication number: 20190103155Abstract: There is provided a multiple data rate memory configured to implement first and second memory accesses within a single cycle of an external clock signal. The memory comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to at least one local bit line, the at least one local bit line of each memory cell group being connected to a local-to-global interface circuit. The local-to-global interface circuit is configured to control the state of at least one first global bit line in dependence upon the state of the at least one local bit line during the first memory access and to control the state of at least one second global bitline in dependence upon the state of the at least one local bit line during the second memory access.Type: ApplicationFiled: February 28, 2017Publication date: April 4, 2019Inventors: Stefan COSEMANS, Bram ROOSELEER