Abstract: An integrated circuit is provided. The integrated circuit includes a central processing unit built to process data and an output pin of the integrated circuit to provide processed data at the output pin to an external device connected to the output pin and a driver for the output pin with an output MOSFET of the driver connected to the output pin to provide the processed data with the power specified for the output pin. The driver includes a dynamic driver stage built to switch the output MOSFET between its conductive and non-conductive condition and a static driver stage built to maintain the condition of the output MOSFET until the dynamic driver stage switches the condition.

Abstract: An integrated circuit is provided. The integrated circuit includes a central processing unit built to process data and an output pin of the integrated circuit to provide processed data at the output pin to an external device connected to the output pin and a driver for the output pin with an output MOSFET of the driver connected to the output pin to provide the processed data with the power specified for the output pin. The driver includes a dynamic driver stage built to switch the output MOSFET between its conductive and non-conductive condition and a static driver stage built to maintain the condition of the output MOSFET until the dynamic driver stage switches the condition.

Abstract: The invention is notably directed to a hardware system (1) designed to implement an artificial neural network (ANN). The hardware system basically includes a neural processing apparatus (15), e.g., involving as crossbar array structure, one or more lookup table circuits (17), and one or more processing units (18). The neural processing apparatus is configured to implement M artificial neurons, where M?1. The lookup table circuits are configured to implement a lookup table (LUT). The system further includes M? processing units, where M?M??1. Each processing unit is connected by at least one neuron, in order to be able to access a first value outputted by each connected neuron. In addition, each processing unit is connected to a LUT circuit, in order to efficiently access parameter values of a set of parameters from the LUT. Finally, each processing unit is configured to output a second value, corresponding to a value of a mathematical function taking said first value as argument.

Abstract: The present document relates to oscillator circuits and a method. An oscillator circuit generates an oscillating voltage signal, wherein the crystal has a first electrode and a second electrode. The oscillator circuit has a power source with a supply terminal and a reference terminal. The oscillator circuit has a switching circuit arranged between the power source and the crystal. The switching circuit, in a start-up phase, alternately connects the supply terminal of the power source to the first and second electrode of the crystal such that an amplitude of the oscillating voltage signal is increased.

Abstract: A fast start-up oscillator circuit to reduce a start-up time of a crystal oscillator is presented. The circuit contains a crystal resonator to output a first oscillation signal and a tunable RC oscillator to output a second oscillation signal. A driver is coupled between the tunable RC oscillator and the crystal resonator The driver transfers the second oscillation signal output from the tunable RC oscillator to the crystal resonator. The driver drives the crystal resonator, and a feedback circuit connected between the crystal resonator and the tunable RC oscillator to align a phase of the tunable RC oscillator with a phase of the crystal resonator based on the oscillation signal output by the crystal resonator.