Abstract: A vertically stacked image sensor with HDR imaging functionality and a method of operating the same are disclosed. The image sensor comprises, a first substrate, a pixel array organized into a plurality of pixel subarrays, of which each pixel comprises a photoelectric element for integrating a photocharge during each one of a plurality of subframe exposures, a transfer gate and a buffered charge-voltage converter. A first charge accumulation element of the charge-voltage converter is operatively connectable to at least one second charge accumulation element through a gain switch. The image sensor comprises control circuitry configured to trigger a partial or a complete transfer of the and to time-interleave at least two rolling shutter control sequences. Separate readout blocks are provided on the second substrate for each pixel subarray, each comprising in a pipelined architecture an A/D conversion unit, a pixel memory logic and a pixel memory unit.

Abstract: A vertically stacked image sensor with HDR imaging functionality and a method of operating the same are disclosed. The image sensor comprises, a first substrate, a pixel array organized into a plurality of pixel subarrays, of which each pixel comprises a photoelectric element for integrating a photocharge during each one of a plurality of subframe exposures, a transfer gate and a buffered charge-voltage converter. A first charge accumulation element of the charge-voltage converter is operatively connectable to at least one second charge accumulation element through a gain switch. The image sensor comprises control circuitry configured to trigger a partial or a complete transfer of the and to time-interleave at least two rolling shutter control sequences. Separate readout blocks are provided on the second substrate for each pixel subarray, each comprising in a pipelined architecture an A/D conversion unit, a pixel memory logic and a pixel memory unit.

Abstract: A shared-pixel circuit includes first and second pixel cells. The pixel cells comprise a photosensitive element, a charge storage area operatively connectable to the photosensitive element, an amplification transistor, and a select switch coupled between the amplification transistor and a column bus. The amplification transistors of the first and second pixel cells are arranged to form an input pair of a differential amplifier configured for receiving one of a first and second sensing signal, representative of the charge stored in the charge storage area of the first and second pixel cells respectively, and an analog signal having a ramped signal portion, as a first input signal, receiving the other one of the first and second sensing signal and the analog signal as a second input signal, comparing the first input signal to the second input signal, and generating a bi-stable output signal based on the comparing of the input signals.

Abstract: An image sensor (10) comprises an array of pixels (11) having a subset of pixels (12). The subset of pixels (12) comprises a first and a second pixel (20, 30), wherein the first and the second pixel (20, 30) each comprises a pinned photodiode (21, 31), a sense node (22, 32), a transfer gate (23, 33) coupled to the pinned photodiode (21, 31) and the sense node (22, 32), and a connection switch (24, 34) coupled to the sense node (22, 32). The subset of pixels (12) further comprises a common reset node (40) such that the connection switch (24, 34) of the first and the second pixel (20, 30) are coupled to the common reset node (40), and a single reset transistor (41) providing a reset voltage (VRES) to the common reset node (40). The first and the second pixel (20, 30) share the single reset transistor (41).

Abstract: An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N?2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

Abstract: An analog-to-digital conversion apparatus 10 comprises a plurality of analog-to-digital converters 30 and a ramp generator 20. Each of the analog-to-digital converters 30 comprises an analog signal input for receiving an analog signal level and a ramp signal input. A control stage is arranged to compare the ramp signal with the analog signal level and, based on the comparison, to enable a counter provided at the analog-to-digital converter or to latch a digital value received from a counter. The control stage comprises a comparator in the form of a first differential amplifier with a first branch connected to the input for receiving the ramp signal, a second branch connected to the analog signal input and an output, and a biasing current source for biasing the first differential amplifier. A feedback circuit controls the biasing current source.

Abstract: A pixel structure comprises a photo-sensitive element for generating charge in response to incident light. A first transfer gate is connected between the photo-sensitive element and a first charge conversion element. A second transfer gate is connected between the photo-sensitive element and a second charge conversion element. An output stage outputs a first value related to charge at the first charge conversion element and outputs a second value related to charge at the second charge conversion element. A controller controls operation of the pixel structures and causes a pixel structure.

Abstract: An analog-to-digital conversion apparatus 10 comprises a plurality of analog-to-digital converters 30 and a ramp generator 20. Each of the analog-to-digital converters 30 comprises an analog signal input for receiving an analog signal level and a ramp signal input. A control stage is arranged to compare the ramp signal with the analog signal level and, based on the comparison, to enable a counter provided at the analog-to-digital converter or to latch a digital value received from a counter. The control stage comprises a comparator in the form of a first differential amplifier with a first branch connected to the input for receiving the ramp signal, a second branch connected to the analog signal input and an output, and a biasing current source for biasing the first differential amplifier. A feedback circuit controls the biasing current source.

Abstract: An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N?2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

Abstract: A pixel structure comprises a photo-sensitive element for generating charge in response to incident light. A first transfer gate is connected between the photo-sensitive element and a first charge conversion element. A second transfer gate is connected between the photo-sensitive element and a second charge conversion element. An output stage outputs a first value related to charge at the first charge conversion element and outputs a second value related to charge at the second charge conversion element. A controller controls operation of the pixel structures and causes a pixel structure.