Patents by Inventor Brandi M. Jones
Brandi M. Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11386231Abstract: Methods and systems for context-based mobile device feature control are provided. One method comprises determining, with a mobile device, one or more contexts corresponding to the mobile device; selecting, from a predetermined set of security protocols, a security protocol corresponding to the determined one or more contexts; and adjusting a permission setting for one or more functional features of the mobile device based upon the selected security protocol. One apparatus comprises one or more features configure to input data, output data, transform data, or a combination thereof; and a controller configured to: determine one or more contexts corresponding to the mobile computing device, to select, from a predetermined set of security protocols, a security protocol corresponding to the determined one or more contexts, and to adjust a permission setting for the one or more functional features based upon the selected security protocol.Type: GrantFiled: July 27, 2020Date of Patent: July 12, 2022Assignee: Micron Technology, Inc.Inventors: Aparna U. Limaye, Lindsay Hamilton, Carla L. Christensen, Cipriana Forgy, Brandi M. Jones
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Publication number: 20210200885Abstract: Methods and systems for context-based mobile device feature control are provided. One method comprises determining, with a mobile device, one or more contexts corresponding to the mobile device; selecting, from a predetermined set of security protocols, a security protocol corresponding to the determined one or more contexts; and adjusting a permission setting for one or more functional features of the mobile device based upon the selected security protocol. One apparatus comprises one or more features configure to input data, output data, transform data, or a combination thereof; and a controller configured to: determine one or more contexts corresponding to the mobile computing device, to select, from a predetermined set of security protocols, a security protocol corresponding to the determined one or more contexts, and to adjust a permission setting for the one or more functional features based upon the selected security protocol.Type: ApplicationFiled: July 27, 2020Publication date: July 1, 2021Inventors: Aparna U. Limaye, Lindsay Hamilton, Carla L. Christensen, Cipriana Forgy, Brandi M. Jones
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Patent number: 8437195Abstract: Some embodiments include apparatus, systems, and methods having a voltage generator to generate a voltage, a memory cell including a storage node associated with a storage node voltage, and a power controller to provide a signal to the voltage generator such that the voltage generated by the voltage generator rises from a voltage less than a reference voltage to a voltage less than the storage node voltage, and such that the voltage generated by the voltage generator is less than or equal to the storage node voltage, at least partially in response to the apparatus entering into a mode. Other embodiments are described.Type: GrantFiled: January 23, 2012Date of Patent: May 7, 2013Assignee: Micron Technology, Inc.Inventors: Yutaka Ito, Adrian J. Drexler, Brandi M. Jones
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Publication number: 20120188831Abstract: Some embodiments include apparatus, systems, and methods having a voltage generator to generate a voltage, a memory cell including a storage node associated with a storage node voltage, and a power controller to provide a signal to the voltage generator such that the voltage generated by the voltage generator rises from a voltage less than a reference voltage to a voltage less than the storage node voltage, and such that the voltage generated by the voltage generator is less than or equal to the storage node voltage, at least partially in response to the apparatus entering into a mode. Other embodiments are described.Type: ApplicationFiled: January 23, 2012Publication date: July 26, 2012Inventors: Yutaka Ito, Adrian J. Drexler, Brandi M. Jones
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Patent number: 8102715Abstract: Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.Type: GrantFiled: May 4, 2011Date of Patent: January 24, 2012Assignee: Micron Technology, Inc.Inventors: Yutaka Ito, Adrian J. Drexler, Brandi M. Jones
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Publication number: 20110205813Abstract: Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.Type: ApplicationFiled: May 4, 2011Publication date: August 25, 2011Inventors: Yutaka Ito, Adrian J. Drexler, Brandi M. Jones
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Patent number: 7940569Abstract: Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.Type: GrantFiled: February 2, 2010Date of Patent: May 10, 2011Assignee: Micron Technology, Inc.Inventors: Yutaka Ito, Adrian J. Drexler, Brandi M. Jones
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Publication number: 20100135065Abstract: Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.Type: ApplicationFiled: February 2, 2010Publication date: June 3, 2010Applicant: Micron Technology, Inc.Inventors: Yutaka Ito, Adrian J. Drexler, Brandi M. Jones
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Patent number: 7656720Abstract: Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.Type: GrantFiled: November 7, 2007Date of Patent: February 2, 2010Assignee: Micron Technology, Inc.Inventors: Yutaka Ito, Adrian J. Drexler, Brandi M. Jones
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Publication number: 20090116328Abstract: Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.Type: ApplicationFiled: November 7, 2007Publication date: May 7, 2009Inventors: Yutaka Ito, Adrian J. Drexler, Brandi M. Jones