Abstract: A method, system and computer program product are provided for implementing enhanced net routing for congestion resolution of non-rectangular or rectangular hierarchical macro designs of an integrated circuit chip. Congested macro nets near a macro boundary are identified. Wiring channels are reserved outside the macro boundary, allowing congested macro nets to be routed outside the physical boundary of the macro while still being logically contained within the macro.

Abstract: A method, system and computer program product are provided for implementing enhanced net routing for congestion resolution of non-rectangular or rectangular hierarchical macro designs of an integrated circuit chip. Congested macro nets near a macro boundary are identified. Wiring channels are reserved outside the macro boundary, allowing congested macro nets to be routed outside the physical boundary of the macro while still being logically contained within the macro.

Abstract: A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

Abstract: A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

Abstract: In a method of generating clock signals for a level-sensitive scan design latch, at least one test input signal is transmitted to a plurality of splitter leaves. Once the test input signal is stabilized at each of the splitter leaves, generating a shaped oscillator clock signal having a predetermined pattern of pulses from a central root is generated. At the plurality of splitter leaves, the test input signal is logically combined with the shaped oscillator clock signal, thereby generating a first latch clock signal and a second latch clock signal. The logically combining action includes applying a delay of less than one clock cycle to the shaped oscillator clock signal to generate a delayed oscillator clock signal; logically combining the delayed oscillator clock signal with a second signal so as to generate the first latch clock signal; and logically combining the shaped oscillator clock signal with a third signal so as to generate the second latch clock signal.

Abstract: In a method of generating clock signals for a level-sensitive scan design latch, at least one test input signal is transmitted to a plurality of splitter leaves. Once the test input signal is stabilized at each of the splitter leaves, generating a shaped oscillator clock signal having a predetermined pattern of pulses from a central root is generated. At the plurality of splitter leaves, the test input signal is logically combined with the shaped oscillator clock signal, thereby generating a first latch clock signal and a second latch clock signal. The logically combining action includes applying a delay of less than one clock cycle to the shaped oscillator clock signal to generate a delayed oscillator clock signal; logically combining the delayed oscillator clock signal with a second signal so as to generate the first latch clock signal; and logically combining the shaped oscillator clock signal with a third signal so as to generate the second latch clock signal.

Abstract: A method, system and computer-readable medium are presented for creating unique clock waveform checking commands for an event simulator to validate that the logical creation matches the timing definitions. The method includes selecting one or more clock signals for validation; specifying timing definitions of the selected clock signals; automatically categorizing the selected clock signals based on their synchrony; automatically matching each selected clock signal to a corresponding clock cycle by parsing the specified timing definitions; specifying one or more test cases for an event simulator, wherein the test cases simulate logic for generating each selected clock signal; validating that the logic for generating each selected clock signal matches the specified timing definitions for each selected clock signal.