Abstract: Embodiments of the present disclosure provide an apparatus for providing a combined tap cell and spare cell in a logic design. An integrated circuit contains a plurality of logic cells that are arranged in a series of columns and rows and that include one or more transistors. A first cell includes a logic portion including one or more transistors, and a tap portion. The tap portion provides tap connectivity to the one or more transistors of the subset of the plurality of logic cells, and to the one or more transistors of the logic portion.

Abstract: An integrated circuit including a plurality of memory circuits and a plurality of logic circuits. The plurality of memory circuits is arranged on a die along a plurality of rows and a plurality of columns. Each memory circuit includes a plurality of memory cells. The plurality of logic circuits is arranged on the die between the plurality of memory circuits along the plurality of rows and the plurality of columns. The plurality of logic circuits is configured to communicate with one or more of the memory circuits.

Abstract: In one embodiment, an integrated circuit (IC) is provided with a thermal diode and a constant current source. In this embodiment, the saturation current of the diode may be determined by means external to the IC. During normal operation of the IC, the constant current source drives a current to the diode, and the forward bias voltage of the diode is used as a temperature indicator. In another embodiment, an IC is provided with a pair of thermal diodes and a constant current source. During normal operation of the IC, each of the diodes receives a current of different magnitude from the constant current source, and a comparison of the diodes' forward bias voltages is used as a temperature indicator.