Abstract: An apparatus includes at least one processing device configured to obtain samples of an input signal to be amplified and, in real-time, pre-distort at least some of the samples using pre-distortion values from at least one lookup table. The pre-distorted samples are to be converted into an analog signal that is amplified by at least one power amplifier. The pre-distortion values at least partially compensate for a non-linear operation of the at least one power amplifier. The at least one processing device is also configured to compare an output signal generated by the at least one power amplifier to an expected signal to identify errors between the output and expected signals. The at least one processing device is further configured to update one or more pre-distortion values in the at least one lookup table based on the identified errors.

Abstract: An apparatus includes at least one processing device configured to obtain samples of an input signal to be amplified and, in real-time, pre-distort at least some of the samples using pre-distortion values from at least one lookup table. The pre-distorted samples are to be converted into an analog signal that is amplified by at least one power amplifier. The pre-distortion values at least partially compensate for a non-linear operation of the at least one power amplifier. The at least one processing device is also configured to compare an output signal generated by the at least one power amplifier to an expected signal to identify errors between the output and expected signals. The at least one processing device is further configured to update one or more pre-distortion values in the at least one lookup table based on the identified errors.

Abstract: A method includes receiving, at a field programmable gate array (FPGA), one or more Ethernet packets of a message including control or status information associated with the FPGA. The method also includes determining, by the FPGA, a payload of each packet by removing at least one Ethernet header from the packet. The method further includes removing, by the FPGA, a User Datagram Protocol (UDP) header from each packet and determining UDP header metadata. The method also includes converting, by the FPGA based on the UDP header metadata, the packets to a read or write message associated with one or more registers of the FPGA. In addition, the method includes performing, by the FPGA, a read or write of the one or more registers of the FPGA according to the read or write message.

Abstract: A method includes receiving, at a field programmable gate array (FPGA), one or more Ethernet packets of a message including control or status information associated with the FPGA. The method also includes determining, by the FPGA, a payload of each packet by removing at least one Ethernet header from the packet. The method further includes removing, by the FPGA, a User Datagram Protocol (UDP) header from each packet and determining UDP header metadata. The method also includes converting, by the FPGA based on the UDP header metadata, the packets to a read or write message associated with one or more registers of the FPGA. In addition, the method includes performing, by the FPGA, a read or write of the one or more registers of the FPGA according to the read or write message.