Abstract: An interface controller for a communications network port that includes support for an efficient client/server protocol for exchanging data between client computers and target mass storage devices. The interface controller includes support to allow a server computer to forward a read or write command from a client computer to a target mass storage device containing the identification of a client computer as the source of the read or write command. Interface controller support also allows a clients computer to receive response to messages elicited by a read and write command transmitted to a server computer directly from a target mass storage device by copying the identification of the mass storage target device into a data structure within the interface controller to which subsequent identifications within subsequent data and status messages received from the target mass storage device are compared.

Abstract: A method and system, implemented in hardware, for quickly and efficiently reassembling Fibre Channel data sequence data received by a Fibre Channel port in host memory buffers. The host memory buffers are referenced by a transaction status block allocated and initialized by the host. The transaction status block is referenced by the Fibre Channel port during transfer of data received in each Fibre Channel data frame of the Fibre Channel data sequence. The host memory buffers may be or arbitrary size and need only be byte aligned. The host computer can specify any number of host memory buffers by appropriate initialization of the transaction status block.

Abstract: An improved local area network interfacing system. The inventive system includes a frontplane circuit for connecting the interfacing system to a local area network and a backplane circuit for connecting the interfacing system to a host. A first internal bus is included for providing communication between the backplane circuit and the frontplane circuit. A processor is included for controlling the operation of the interfacing system. A second internal bus is included for providing communication between the processor and associated memory. An internal bus control circuit facilitates and controls communication between the first internal bus and the second internal bus. The dual internal busses of interfacing system of the present invention afford high speed operation with an inexpensive processor by allowing for input and output operations to be completed without being impeded by processor operations.