Abstract: A home site fuel monitor device in conjunction with a remote central site system to provide accurate fuel usage data used in planning fuel deliveries. The fuel monitor device is an internet based, compact, and low cost home heating site monitor device that is easily installed in the home heating site without modification to the home site's heating system. The monitor device includes a microprocessor which measures heating system run times using real time clock values. The microprocessor computes heating system fuel usage and the rate of fuel usage using heating system run times and heating burner parameters down loaded from the remote central site system. The monitor device continuously adjusts or recalibrates the rate of fuel usage defined as a burn coefficient value to coincide with the latest delivery information received from the central site system which results in increased accuracy over time.

Abstract: A home site fuel monitor device in conjunction with a remote central site system to provide accurate fuel usage data used in planning fuel deliveries. The fuel monitor device is U an internet based, compact, and low cost home heating site monitor device that is easily installed in the home heating site without modification to the home site's heating system. The monitor device includes a microprocessor which measures heating system run times using real time clock values. The microprocessor computes heating system fuel usage and the rate of fuel usage using heating system run times and heating burner parameters down loaded from the remote central site system. The monitor device continuously adjusts or recalibrates the rate of fuel usage defined as a burn coefficient value to coincide with the latest delivery information received from the central site system which results in increased accuracy over time.

Abstract: An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

Abstract: An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

Abstract: An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.