Abstract: A latch circuit providing isolated input current paths includes a pair of input transistors that receive a differential input signal. A plurality of steering transistors receive a portion of a differential clock signal. The latch circuit includes a positive output node and a negative output node. A first bypass input current path is associated with the first input transistor and is electrically isolated from the positive output node and the negative output node. A second bypass input current path associated with the second input transistor is also electrically isolated from the positive output node and the negative output node. In a latched state, the clock signal is operative to selectively bias the plurality of steering transistors such that current is steered to one of the first input current path or the second input current path, thereby being isolated from the output nodes.

Abstract: A reconfigurable wideband analog-to-digital converter (ADC) system comprising a first converter stage including a first sample and hold circuit for sampling an input signal, a first ADC configured to generate a digital representation of the sampled input signal from the first sample and hold circuit, and a first digital-to-analog converter (DAC) responsive to the output of the first ADC and configured to generate an analog representation of the digital representation of the sampled input signal. A control processor is provided and configured to generate a digital control signal. A current control circuit is responsive to the digital control signal for generating an analog current control signal for selectively altering a characteristic of at least one of the first ADC and the first DAC.

Abstract: An integrated circuit includes a clock distribution circuit and a logic block circuit. The clock distribution circuit is segregated from the logic block circuit to restrict contributors to phase noise to the clock distribution section of the circuit. The clock distribution circuit includes a front-end amplifier which buffers a clock input signal to a differential clock signal. The front-end amplifier is configured with as few components as possible and the components are selected for high current density and sized to minimize contributions to phase noise in the clock distribution circuit. The clock distribution circuit further includes an output latch circuit that receives the output signal of the logic block circuit and the low phase noise differential clock input signal from the front-end amplifier circuit. The output latch circuit re-clocks the final output of the integrated circuit. The output is representative of the output values determined by the logic block circuit.

Abstract: A vector sum circuit for producing a radio frequency (RF) output at a selectable phase offset includes an RF input configured to receive a differential pair RF input. A quadrature network produces an additional pair of RF inputs whose phase is advanced 90 degrees (90°) with reference to the first differential pair RF input, thereby producing four RF input signals offset at 0°, 90°, 180° and 270°. For each RF input signal, a set of three cascodes, having a plurality of NPN transistors and each emitter being commonly connected to an RF input. The first cascode steers current to a first output node, the second cascode steers current to a second output node and the third cascode shunts current to the voltage rail. By selectively steering current from the quadrature RF inputs to a selected output, an output signal having a desired phase shift is achieved.

Abstract: A reconfigurable wideband analog-to-digital converter (ADC) system comprising a first converter stage including: a first signal path including a first sample and hold circuit responsive to an input signal for sampling the input signal at a first resolution; a second signal path arranged parallel to the first signal path and including a second sample and hold circuit responsive to the input signal for sampling the input signal at a second resolution; and a control circuit arranged in series with the first and second signal paths and configured to isolate one of the first and second signal paths from an output of the control circuit in response to a control signal.

Abstract: A flash analog to digital converter (ADC) provides a temperature compensated trim current by applying a first temperature compensated reference current across a replica resistor ladder. The reference current is mirrored to a trim digital to analog converter, which outputs a fractional portion of the temperature compensated reference current. The proportional trim current is then fed back to the reference current to provide a trimmed temperature compensated reference current. The trimmed reference current is mirrored across the output resistor ladder providing a trimmed current in which the trim varies along with temperature changes due to the trim current being a proportion of the temperature compensated reference current. A proportional trim current which varies with temperature changes is applied to the gain current trim and mismatch current trim in a DAC of a quantizing stage of a sub-ranging ADC.

Abstract: A reconfigurable wideband analog-to-digital converter (ADC) system comprising a first converter stage having a first signal path including a first sample and hold circuit for sampling an input signal at a first resolution, and a second signal path responsive to the input signal and arranged in parallel with the first signal path. The second signal path includes a second sample and hold circuit for sampling the input signal at a second resolution. A first ADC is also included for generating a digital representation of the input signal sampled by the first converter stage. A control processor is arranged between outputs of the first and second sample and hold circuits and the input of the ADC for selectively providing the signal sampled by one of the first or second sample and hold circuit to the input of the ADC.

Abstract: A clocking scheme for a reconfigurable wideband analog-to-digital converter (ADC) including a plurality of Delay Locked Loops (DLLs) arranged in parallel. Each DLL is responsive to an input clock signal and configured to selectively generate a plurality of output clock signals for controlling the operation of the ADC.

Abstract: A variable gain amplifier having a stacked configuration of cascode connected groups of NPN transistors is arranged in a compact schematic design. A differential radio frequency input signal is received at input nodes which is directed to a fine gain control circuit which conducts at least a portion of the received RF signal to a coarse gain control circuit that is downstream of the fine gain control circuit. The coarse gain control circuit steers current to an output node. Gain control circuits include transistor pairs. The base electrodes of each transistor pair receive inverse control signals which cause only one of the transistors in the transistor pair to conduct current. Collector electrodes of each first transistor of the pair is coupled to a downstream node in the VGA circuit, while collector electrodes of each second transistor of the pair is shunted to the voltage rail.

Abstract: A variable gain amplifier includes a first transistor having a base for receiving a radio frequency (“RF”) input signal. A first differential transistor pair is coupled in parallel to a second transistor. The first differential transistor pair and the second transistor are coupled to a collector of the first transistor and to an output node of the first variable gain amplifier. Each transistor of the first differential transistor pair is configured to receive a control signal at its respective gate for adjusting a gain of the variable gain amplifier.

Abstract: A phase shifter comprises a differential quadrature all-pass filter (QAF) including a balanced input port and two balanced output ports. A quadrature phase shift is manifested between the balanced output ports. The phase shifter also comprises a resistance-capacitance polyphase filter (PPF) section defining two balanced input ports and two balanced output ports. The balanced input ports of the PPF are coupled to the balanced output ports of the QAF. The combination exhibits broad bandwidth and relatively low ohmic loss.