Patents by Inventor Brandon R. Kam

Brandon R. Kam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit and method for on-chip jitter measurement
    Patent number: 8385394
    Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: February 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brandon R. Kam, Stephen D. Wyatt
  • CIRCUIT AND METHOD FOR ON-CHIP JITTER MEASUREMENT
    Publication number: 20120134403
    Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.
    Type: Application
    Filed: February 2, 2012
    Publication date: May 31, 2012
    Applicant: International Business Machines Corporation
    Inventors: Brandon R. Kam, Stephen D. Wyatt
  • Circuit and method for on-chip jitter measurement
    Patent number: 8126041
    Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: February 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brandon R. Kam, Stephen D. Wyatt
  • CIRCUIT AND METHOD FOR ON-CHIP JITTER MEASUREMENT
    Publication number: 20090102452
    Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.
    Type: Application
    Filed: October 19, 2007
    Publication date: April 23, 2009
    Inventors: Brandon R. Kam, Stephen D. Wyatt
  • Circuit and method for on-chip jitter measurement
    Patent number: 7339364
    Abstract: An improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal, the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.
    Type: Grant
    Filed: June 19, 2006
    Date of Patent: March 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Brandon R. Kam, Stephen D. Wyatt
  • CIRCUIT AND METHOD FOR ON-CHIP JITTER MEASUREMENT
    Publication number: 20080012549
    Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.
    Type: Application
    Filed: June 19, 2006
    Publication date: January 17, 2008
    Inventors: Brandon R. Kam, Stephen D. Wyatt