Abstract: An input buffer is presented for buffering an input signal having a voltage magnitude which alternates between a first voltage level and a second voltage level, where the first and second voltage levels may vary over time. In one embodiment, the input buffer includes a first and second detector circuits, an average generator circuit, and a differential amplifier. The first detector circuit receives the input signal and produces a first signal having a magnitude indicative of the first voltage level. The second detector circuit receives the input signal and produces a second signal having a magnitude indicative of the second voltage level. The average generator circuit receives the first and second signals, and uses the magnitudes of the first and second signals to produce a third signal having a magnitude indicative of a third voltage level substantially mid way between the first voltage level and the second voltage level. The third voltage level defines a variable an automatically adjusted “switching point”.

Abstract: An input buffer is presented for buffering an input signal having a voltage magnitude which alternates between a first voltage level and a second voltage level, where the first and second voltage levels may vary over time. In one embodiment, the input buffer includes a first and second detector circuits, an average generator circuit, and a differential amplifier. The first detector circuit receives the input signal and produces a first signal having a magnitude indicative of the first voltage level. The second detector circuit receives the input signal and produces a second signal having a magnitude indicative of the second voltage level. The average generator circuit receives the first and second signals, and uses the magnitudes of the first and second signals to produce a third signal having a magnitude indicative of a third voltage level substantially mid way between the first voltage level and the second voltage level. The third voltage level defines a variable an automatically adjusted “switching point”.

Abstract: A differential buffer has a bias current that is gated by a signal associated with the buffer, such as its input or output. In a preferred embodiment, the bias current is low when the input is in a steady state, but increases as the input switches, to provide high bias current for faster switching of the output. The input preferably is monitored by a rising edge detector and a falling edge detector to turn on the high bias current as the input switches. The output preferably is also monitored, to turn off the high bias current after the output has finished switching, and a steady state has resumed.

Abstract: A differential driver circuit includes an output connection equilibration circuit. The equilibration circuit balances the output connection voltages to reduce current consumption when transitioning the driver between data states. Equilibrating the differential driver can reduce the current consumption experienced by prior circuits. In one embodiment, the driver circuit is placed in a tri-state condition while the output connections are electrically shorted together. After the output connection have reduced their voltage differential, or reached an intermediate equal level, the driver circuit(s) are activated.