Abstract: Techniques for the estimation of sample-time and gain mismatch errors in a two-channel time interleaved analog to digital converter that are devoid of any multiplication operation. In a sample-time mismatch error evaluation, the signs and the absolute values from the two ADCs are used to provide an estimate of the sample-time mismatch error. In a gain error estimation algorithm, the absolute values of the outputs from the two ADCs are subtracted and accumulated. The errors can then be corrected, in a preferred embodiment, using suitable adaptive sample time and gain correction techniques.

Abstract: A wide band analog-to-digital converter used in a frequency multiplexed communication system. The converter includes a plurality, M, of time-interleaved analog-to-digital converter subunits (ADC subunits). The sampling rate, FS1, of the M ADC subunits is selected to locate one or more integer multiples of a Nyquist frequency of a respective subunit ADC in one or more guard bands, and/or such that one or more integer multiples of FS1 are also located in the guard bands.

Abstract: Techniques for the estimation of sample-time and gain mismatch errors in a two-channel time interleaved analog to digital converter that are devoid of any multiplication operation. In a sample-time mismatch error evaluation, the signs and the absolute values from the two ADCs are used to provide an estimate of the sample-time mismatch error. In a gain error estimation algorithm, the absolute values of the outputs from the two ADCs are subtracted and accumulated. The errors can then be corrected, in a preferred embodiment, using suitable adaptive sample time and gain correction techniques.

Abstract: A wide band analog-to-digital converter used in a frequency multiplexed communication system. The converter includes a plurality, M, of time-interleaved analog-to-digital converter subunits (ADC subunits). The sampling rate, FS1, of the M ADC subunits is selected to locate one or more integer multiples of a Nyquist frequency of a respective subunit ADC in one or more guard bands, and/or such that one or more integer multiples of FS1 are also located in the guard bands.

Abstract: A method and apparatus are described that detect and correct for over-saturation lighting conditions in a CMOS Image Sensor.

Abstract: Method and apparatus for dynamically biasing pixels in an image sensor array to remove pixel offset variations.

Abstract: A CMOS image sensor circuit includes an array of sensing elements which integrate electrical charge according to the light intensity thereon. In order to measure the accumulated charge voltage at the individual sensing elements, and thus obtain the image data from the array, a sampling circuit is provided. The sampling circuit operates using a high-gain amplification stage and an auto-zero amplifier to perform correlated double sampling, which enables non-linear influences which may arise in the array to be reduced in the measuring process. The sampling circuit can also include a sample and hold circuit arranged to account for a feed-through effect arising from pre-charge circuitry in the sensing elements. The sample and hold circuit can be included within the feed-back loop of the high-gain amplification stage for further increases in linear performance.

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC.

Abstract: A method and apparatus are described that detect and correct for over-saturation lighting conditions in a CMOS Image Sensor.

Abstract: Semiconductor photo sensor and semiconductor wafer processing designs are disclosed. The disclosed designs provide significantly improved photo sensor performance within the framework of a CMOS process. CMOS compatible fabrication procedures are presented, that enable tailoring of the 3-dimensional doping profile and defect structure within a photo sensor, to optimize light detection efficiency and minimize noise from dark current.

Abstract: The method of mounting a semiconductor device 200 on a supporting structure 101, the semiconductor device having a surface 201 including a defined area 202 for receiving photons and a plurality of conductors 203/204 for establishing connections to the device. An aperture 301 is formed through the supporting structure, the aperture sized to correspond to a size of the defined area of the semiconductor device. Conductors 302 are formed on the supporting structure adjacent to the aperture in a pattern corresponding to the pattern of the conductors on the semiconductor device. The semiconductor device is mounted to the supporting structure such that the conductors on the semiconductor device contact the conductors on the supporting structure where the defined area of the semiconductor device is exposed to photons through the aperture.