Patents by Inventor Breandán Pol Og Ó hAnnaidh

Breandán Pol Og Ó hAnnaidh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11563084
    Abstract: A bipolar junction transistor is provided with an emitter structure that is positioned above the upper surface of the base region. The thickness of the emitter and the interfacial oxide thickness between the emitter and the base is configured to optimize a gain for a given type of transistor. A method of fabricating PNP and NPN transistors on the same substrate using a complementary bipolar fabrication process is provided. The method enables the emitter structure for the NPN transistor to be defined separately to that of the PNP transistor. This is achieved by epitaxially growing the emitter layer for the PNP transistor and growing the emitter layer for the NPN transistor in a thermal furnace.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: January 24, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: Edward John Coyne, Alan Brannick, Shane Tooher, Breandán Pol Og Ó hAnnaidh, Catriona Marie O'Sullivan, Shane Patrick Geary
  • Patent number: 11355585
    Abstract: A charge control structure is provided for a bipolar junction transistor to control the charge distribution in the depletion region extending into the bulk collector region when the collector-base junction is reverse-biased. The charge control structure comprises a lateral field plate above the upper surface of the collector and dielectrically isolated from the upper surface of the collector and a vertical field plate which is at a side of the collector and is dielectrically isolated from the side of the collector. The charge in the depletion region extending into the collector is coupled to the base as well as the field-plates in the charge-control structure, instead of only being coupled to the base of the bipolar junction transistor. In this way, a bipolar junction transistor is provided where the dependence of collector current on the collector-base voltage, also known as Early effect, can be reduced.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: June 7, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Edward John Coyne, Alan Brannick, Shane Tooher, Breandán Pol Og Ó hAnnaidh, Catriona Marie O'Sullivan, Shane Patrick Geary
  • Publication number: 20210098575
    Abstract: A charge control structure is provided for a bipolar junction transistor to control the charge distribution in the depletion region extending into the bulk collector region when the collector-base junction is reverse-biased. The charge control structure comprises a lateral field plate above the upper surface of the collector and dielectrically isolated from the upper surface of the collector and a vertical field plate which is at a side of the collector and is dielectrically isolated from the side of the collector. The charge in the depletion region extending into the collector is coupled to the base as well as the field-plates in the charge-control structure, instead of only being coupled to the base of the bipolar junction transistor. In this way, a bipolar junction transistor is provided where the dependence of collector current on the collector-base voltage, also known as Early effect, can be reduced.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Edward John Coyne, Alan Brannick, Shane Tooher, Breandán Pol Og Ó hAnnaidh, Catriona Marie O'Sullivan, Shane Patrick Geary
  • Publication number: 20210098576
    Abstract: A bipolar junction transistor is provided with a multilayer collector structure. The layers of the collector are individually grown in separate epitaxial growth stages. For a PNP transistor, each layer, after it is grown, is doped with a p-type dopant in a dedicated implant stage. By providing separate epitaxial growth stages and separate dopant implant stages for each layer of the collector, the dopant concentration profile in the collector region can be better controlled to optimize the speed and breakdown voltage of a bipolar junction transistor.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Edward John Coyne, Alan Brannick, Shane Tooher, Breandán Pol Og Ó hAnnaidh, Catriona Marie O'Sullivan, Shane Patrick Geary
  • Publication number: 20210098574
    Abstract: A bipolar junction transistor is provided with an emitter structure that is positioned above the upper surface of the base region. The thickness of the emitter and the interfacial oxide thickness between the emitter and the base is configured to optimize a gain for a given type of transistor. A method of fabricating PNP and NPN transistors on the same substrate using a complementary bipolar fabrication process is provided. The method enables the emitter structure for the NPN transistor to be defined separately to that of the PNP transistor. This is achieved by epitaxially growing the emitter layer for the PNP transistor and growing the emitter layer for the NPN transistor in a thermal furnace.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Edward John Coyne, Alan Brannick, Shane Tooher, Breandán Pol Og Ó hAnnaidh, Catriona Marie O'Sullivan, Shane Patrick Geary
  • Patent number: 9362356
    Abstract: A transistor is provided in which an elongate drain region has end portions formed in parts of the transistor where features of the transistor structure have been modified or omitted. These structures lessen the current flow or electric field gradients at the end portions of the drain. This provides a transistor that has improved on-state breakdown performance without sacrificing off state breakdown performance.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: June 7, 2016
    Assignee: Analog Devices Global
    Inventors: Breandan Pol Og O hAnnaidh, Seamus Paul Whiston, Edward John Coyne, William Allan Lane, Donal Peter McAuliffe
  • Publication number: 20160133701
    Abstract: A transistor is provided in which an elongate drain region has end portions formed in parts of the transistor where features of the transistor structure have been modified or omitted. These structures lessen the current flow or electric field gradients at the end portions of the drain. This provides a transistor that has improved on-state breakdown performance without sacrificing off state breakdown performance.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 12, 2016
    Inventors: Breandan Pol Og O hAnnaidh, Seamus Paul Whiston, Edward John Coyne, William Allan Lane, Donal Peter McAuliffe
  • Patent number: 9252260
    Abstract: A semiconductor device having a first layer adjoining a semiconductor layer, and further comprising at least one field modification structure positioned such that, in use, a potential at the field modification structure causes an E-field vector at a region of an interface between the semiconductor and the first layer to be modified.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: February 2, 2016
    Assignee: Analog Devices Global
    Inventors: Edward John Coyne, Breandan Pol Og O hAnnaidh, Seamus P. Whiston, William Allan Lane, Donai P. McAuliffe
  • Publication number: 20150014791
    Abstract: A semiconductor device having a first layer adjoining a semiconductor layer, and further comprising at least one field modification structure positioned such that, in use, a potential at the field modification structure causes an E-field vector at a region of an interface between the semiconductor and the first layer to be modified.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 15, 2015
    Inventors: Edward John Coyne, Breandan Pol Og O hAnnaidh, Seamus P. Whiston, William Allan Lane, Donal P. McAuliffe