Abstract: A data processing system is disclosed utilizing a microprogram memory controller wherein the memory controller may be altered and/or upgraded to accommodate variations in memory systems while maintaining a compatible system-level interface. The memory controller includes a microprogram engine and a resident microprogram stored within nonvolatile memory coupled to the microprogram engine wherein the microprogram engine may utilize the resident microprogram to manage, configure and determine operational modes for a memory subsystem. A variable microprogram may also be loaded within Random Access Memory associated with the microprogram engine and utilized to extend or enhance the operation of the memory controller. The memory controller also preferably utilizes a control interface for providing an interface between the memory controller and the processor, which may be utilized to control the loading of the variable microprogram into the memory controller from an external source.

Abstract: An address decoder is connected to an address bus and comprises a plurality of latches for latching address signals from the address bus. Decode logic is connected to use unlatched addresses from the address bus or latched addresses from the latches. The decoder is selectively operable to decode addresses in two modes, an unlatched mode and a latched mode dependent upon system frequency. The decode logic produces a signal that is transmitted into a state machine for controlling operation thereof.