Patents by Inventor Brendan BARRY

Brendan BARRY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200089506
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve convolution efficiency of a convolution neural network (CNN) accelerator. An example hardware accelerator includes a hardware data path element (DPE) in a DPE array, the hardware DPE including an accumulator, and a multiplier coupled to the accumulator, the multiplier to multiply first inputs including an activation value and a filter coefficient value to generate a first convolution output when the hardware DPE is in a convolution mode, and a controller coupled to the DPE array, the controller to adjust the hardware DPE from the convolution mode to a pooling mode by causing at least one of the multiplier or the accumulator to generate a second convolution output based on second inputs, the second inputs including an output location value of a pool area, at least one of the first inputs different from at least one of the second inputs.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 19, 2020
    Inventors: Sean Power, David Moloney, Brendan Barry, Fergal Connor
  • Patent number: 10572252
    Abstract: A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: February 25, 2020
    Assignee: Movidius Limited
    Inventors: Brendan Barry, Fergal Connor, Martin O'Riordan, David Moloney, Sean Power
  • Patent number: 10521238
    Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: December 31, 2019
    Assignee: Movidius Limited
    Inventors: Brendan Barry, Richard Richmond, Fergal Connor, David Moloney
  • Publication number: 20190370005
    Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.
    Type: Application
    Filed: June 18, 2019
    Publication date: December 5, 2019
    Inventors: David Moloney, Richard Richmond, David Donohoe, Brendan Barry
  • Patent number: 10460704
    Abstract: Systems and methods are provided for rendering of a dual eye-specific display. The system tracks the user's eye movements and/or positions, in some implementations, based on electroencephalography (EEG) of the user, to correctly label the central (foveal) and peripheral (extra-foveal) areas of the display. Foveal data is fully rendered while extra-foveal data is reduced in resolution and, in some implementations, shared between the two displays.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: October 29, 2019
    Assignee: Movidius Limited
    Inventors: Brendan Barry, David Moloney
  • Patent number: 10360040
    Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: July 23, 2019
    Assignee: Movidius, LTD.
    Inventors: David Moloney, Richard Richmond, David Donohoe, Brendan Barry
  • Publication number: 20180349147
    Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.
    Type: Application
    Filed: February 20, 2018
    Publication date: December 6, 2018
    Inventors: David Moloney, Richard Richmond, David Donohoe, Brendan Barry
  • Publication number: 20180246725
    Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.
    Type: Application
    Filed: February 20, 2018
    Publication date: August 30, 2018
    Inventors: Brendan Barry, Richard Richmond, Fergal Connor, David Moloney
  • Patent number: 10001993
    Abstract: A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: June 19, 2018
    Assignee: Linear Algebra Technologies Limited
    Inventors: Brendan Barry, Fergal Connor, Martin O'Riordan, David Moloney, Sean Power
  • Patent number: 9996912
    Abstract: One of the challenges in bringing computational imaging to a mass market is that computational imaging is inherently computationally expensive. The computational challenges associated with computational imaging are apparent with the computation of a histogram of gradient descriptors. Oftentimes, generating a histogram of gradient descriptors involves computing gradients of an image, binning the gradients according to their orientation, and, optionally, normalizing the bins using a non-linear function. Because each of these operations is expensive, the histogram of gradient descriptor computations is generally computationally expensive and is difficult to implement in a power efficient manner for mobile applications. The present application discloses a computing device that can provide a low-power, highly capable computing platform for computing a histogram of gradient descriptors.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: June 12, 2018
    Assignee: Linear Algebra Technologies Limited
    Inventors: Richard Richmond, Cormac Brick, Brendan Barry, David Moloney
  • Publication number: 20180101746
    Abstract: The present application provides a method of corner detection and an image processing system for detecting corners in an image. The preferred implementation is in software using enabling and reusable hardware features in the underlying vector processor architecture. The advantage of this combined software and programmable processor datapath hardware is that the same hardware used for the FAST algorithm can also be readily applied to a variety of other computational tasks, not limited to image processing.
    Type: Application
    Filed: December 8, 2017
    Publication date: April 12, 2018
    Inventors: Cormac Brick, Brendan Barry, Fergal Connor, David Moloney
  • Patent number: 9934043
    Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: April 3, 2018
    Assignee: Linear Algebra Technologies Limited
    Inventors: David Moloney, Richard Richmond, David Donohoe, Brendan Barry
  • Patent number: 9910675
    Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: March 6, 2018
    Assignee: LINEAR ALGEBRA TECHNOLOGIES LIMITED
    Inventors: Brendan Barry, Richard Richmond, Fergal Connor, David Moloney
  • Patent number: 9842271
    Abstract: The present application provides a method of corner detection and an image processing system for detecting corners in an image. The preferred implementation is in software using enabling and reusable hardware features in the underlying vector processor architecture. The advantage of this combined software and programmable processor datapath hardware is that the same hardware used for the FAST algorithm can also be readily applied to a variety of other computational tasks, not limited to image processing.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: December 12, 2017
    Assignee: Linear Algebra Technologies Limited
    Inventors: Cormac Brick, Brendan Barry, Fergal Connor, David Moloney
  • Patent number: 9808548
    Abstract: A regenerable antimicrobial coating with long-lasting efficacy for use in medical applications including implants, medical instruments or devices, and hospital equipment is disclosed. The regenerable antimicrobial coating is derived from a polymer doped with a metal derivative which has been exposed to vapor-phase hydrogen peroxide, wherein hydrogen peroxide is sequestered in or on the doped polymer.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: November 7, 2017
    Assignee: QUICK-MED TECHNOLOGIES, INC.
    Inventors: William Toreki, Rustom Sam Kanga, Bernard Christopher Crampsie, Brendan Barry Wynn
  • Publication number: 20170293346
    Abstract: A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.
    Type: Application
    Filed: December 16, 2016
    Publication date: October 12, 2017
    Inventors: Brendan BARRY, Fergal CONNOR, Martin O'RIORDAN, David MOLONEY, Sean POWER
  • Publication number: 20170287447
    Abstract: Systems and methods are provided for rendering of a dual eye-specific display. The system tracks the user's eye movements and/or positions, in some implementations, based on electroencephalography (EEG) of the user, to correctly label the central (foveal) and peripheral (extra-foveal) areas of the display. Foveal data is fully rendered while extra-foveal data is reduced in resolution and, in some implementations, shared between the two displays.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Applicant: Linear Algebra Technologies Limited
    Inventors: Brendan BARRY, David MOLONEY
  • Patent number: 9727113
    Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: August 8, 2017
    Assignee: LINEAR ALGEBRA TECHNOLOGIES LIMITED
    Inventors: Brendan Barry, Richard Richmond, Fergal Connor, David Moloney
  • Publication number: 20170116718
    Abstract: One of the challenges in bringing computational imaging to a mass market is that computational imaging is inherently computationally expensive. The computational challenges associated with computational imaging are apparent with the computation of a histogram of gradient descriptors. Oftentimes, generating a histogram of gradient descriptors involves computing gradients of an image, binning the gradients according to their orientation, and, optionally, normalizing the bins using a non-linear function. Because each of these operations is expensive, the histogram of gradient descriptor computations is generally computationally expensive and is difficult to implement in a power efficient manner for mobile applications. The present application discloses a computing device that can provide a low-power, highly capable computing platform for computing a histogram of gradient descriptors.
    Type: Application
    Filed: October 31, 2016
    Publication date: April 27, 2017
    Inventors: Richard RICHMOND, Cormac BRICK, Brendan BARRY, David MOLONEY
  • Patent number: 9483706
    Abstract: One of the challenges in bringing computational imaging to a mass market is that computational imaging is inherently computationally expensive. The computational challenges associated with computational imaging are apparent with the computation of a histogram of gradient descriptors. Oftentimes, generating a histogram of gradient descriptors involves computing gradients of an image, binning the gradients according to their orientation, and, optionally, normalizing the bins using a non-linear function. Because each of these operations is expensive, the histogram of gradient descriptor computations is generally computationally expensive and is difficult to implement in a power efficient manner for mobile applications. The present application discloses a computing device that can provide a low-power, highly capable computing platform for computing a histogram of gradient descriptors.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: November 1, 2016
    Assignee: Linear Algebra Technologies Limited
    Inventors: Richard Richmond, Cormac Brick, Brendan Barry, David Moloney