Patents by Inventor Brendan BARRY

Brendan BARRY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170293346
    Abstract: A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.
    Type: Application
    Filed: December 16, 2016
    Publication date: October 12, 2017
    Inventors: Brendan BARRY, Fergal CONNOR, Martin O'RIORDAN, David MOLONEY, Sean POWER
  • Publication number: 20170287447
    Abstract: Systems and methods are provided for rendering of a dual eye-specific display. The system tracks the user's eye movements and/or positions, in some implementations, based on electroencephalography (EEG) of the user, to correctly label the central (foveal) and peripheral (extra-foveal) areas of the display. Foveal data is fully rendered while extra-foveal data is reduced in resolution and, in some implementations, shared between the two displays.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Applicant: Linear Algebra Technologies Limited
    Inventors: Brendan BARRY, David MOLONEY
  • Publication number: 20170116718
    Abstract: One of the challenges in bringing computational imaging to a mass market is that computational imaging is inherently computationally expensive. The computational challenges associated with computational imaging are apparent with the computation of a histogram of gradient descriptors. Oftentimes, generating a histogram of gradient descriptors involves computing gradients of an image, binning the gradients according to their orientation, and, optionally, normalizing the bins using a non-linear function. Because each of these operations is expensive, the histogram of gradient descriptor computations is generally computationally expensive and is difficult to implement in a power efficient manner for mobile applications. The present application discloses a computing device that can provide a low-power, highly capable computing platform for computing a histogram of gradient descriptors.
    Type: Application
    Filed: October 31, 2016
    Publication date: April 27, 2017
    Inventors: Richard RICHMOND, Cormac BRICK, Brendan BARRY, David MOLONEY
  • Publication number: 20160203384
    Abstract: One of the challenges in bringing computational imaging to a mass market is that computational imaging is inherently computationally expensive. The computational challenges associated with computational imaging are apparent with the computation of a histogram of gradient descriptors. Oftentimes, generating a histogram of gradient descriptors involves computing gradients of an image, binning the gradients according to their orientation, and, optionally, normalizing the bins using a non-linear function. Because each of these operations is expensive, the histogram of gradient descriptor computations is generally computationally expensive and is difficult to implement in a power efficient manner for mobile applications. The present application discloses a computing device that can provide a low-power, highly capable computing platform for computing a histogram of gradient descriptors.
    Type: Application
    Filed: January 8, 2015
    Publication date: July 14, 2016
    Inventors: Richard RICHMOND, Cormac BRICK, Brendan BARRY, David MOLONEY
  • Publication number: 20150138405
    Abstract: The disclosed embodiments include an apparatus implemented in a semiconductor integrated chip. The apparatus is configured to operate a composite function, comprising a first function and a second function, on a first patch of an image. The apparatus includes a first function operator configured to operate the first function on the group of pixel values to provide a first processed group of pixel values. The apparatus also includes a delay system configured to maintain the first processed group of pixel values for a predetermined period of time to provide a delayed processed group of pixel values. The apparatus further includes a second function operator configured to operate a second function on at least a second processed group of pixels and the delayed processed group to determine an output of the composite function.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: LINEAR ALGEBRA TECHNOLOGIES LIMITED
    Inventors: David DONOHOE, Brendan BARRY, David MOLONEY, Richard RICHMOND, Fergal CONNOR
  • Publication number: 20150046677
    Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.
    Type: Application
    Filed: November 18, 2013
    Publication date: February 12, 2015
    Applicant: LINEAR ALGEBRA TECHNOLOGIES LIMITED
    Inventors: David MOLONEY, Richard RICHMOND, David DONOHOE, Brendan BARRY
  • Publication number: 20150046675
    Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.
    Type: Application
    Filed: August 12, 2014
    Publication date: February 12, 2015
    Inventors: Brendan BARRY, Richard RICHMOND, Fergal CONNOR, David MOLONEY
  • Publication number: 20150046678
    Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.
    Type: Application
    Filed: November 18, 2013
    Publication date: February 12, 2015
    Applicant: Linear Algebra Technologies Limited
    Inventors: David MOLONEY, Richard RICHMOND, David DONOHOE, Brendan BARRY, Cormac BRICK, Ovidiu Andrei VESA
  • Publication number: 20150046674
    Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.
    Type: Application
    Filed: August 12, 2014
    Publication date: February 12, 2015
    Inventors: Brendan BARRY, Richard RICHMOND, Fergal CONNOR, David MOLONEY
  • Publication number: 20150046673
    Abstract: A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.
    Type: Application
    Filed: August 12, 2014
    Publication date: February 12, 2015
    Inventors: Brendan BARRY, Fergal CONNOR, Martin O'RIORDAN, David MOLONEY, Sean POWER
  • Publication number: 20140348431
    Abstract: The present application provides a method of corner detection and an image processing system for detecting corners in an image. The preferred implementation is in software using enabling and reusable hardware features in the underlying vector processor architecture. The advantage of this combined software and programmable processor datapath hardware is that the same hardware used for the FAST algorithm can also be readily applied to a variety of other computational tasks, not limited to image processing.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 27, 2014
    Applicant: LINEAR ALGEBRA TECHNOLOGIES LIMITED
    Inventors: Cormac BRICK, Brendan BARRY, Fergal CONNOR, David MOLONEY