Abstract: The invention to mismatch and ISI shaping in a data converter. The invention provides a dynamic element matching technique that incorporates both mismatch and inter symbol interference shaping. A digital decoder is provided that controls the number of ‘on’ and ‘off’ transitions so that the resulting signal does not contain noise or distortion. The element selection technique of the invention is suitable for high resolution multi-bit continuous time oversampling data converters.

Abstract: The invention to mismatch and ISI shaping in a data converter. The invention provides a dynamic element matching technique that incorporates both mismatch and inter symbol interference shaping. A digital decoder is provided that controls the number of ‘on’ and ‘off’ transitions so that the resulting signal does not contain noise or distortion. The element selection technique of the invention is suitable for high resolution multi-bit continuous time oversampling data converters.

Abstract: A test system (1) comprises a system-on-chip with a memory (7) for storing sample data; and a dynamic test engine (4) to control input of dynamic test waveforms including sinusoidal waveforms to an ADC under test (15) and to determine device under test dynamic parameters by analysing the samples. A linear test engine (5) determines device under test (15) static parameters, and controls input of ramp input waveforms to the ADC. A test controller (2) performs finite sate machine control of testing including applying test waveforms, dumping samples to the memory (7), and retrieving static and dynamic results. A DAC (3) generates controlled waveform generation under instructions from the test engines, and an interface (10) communicates with an external host. The components are linked with a bus (11) and are modular.

Abstract: A test system (1) comprises a system-on-chip with a memory (7) for storing sample data; and a dynamic test engine (4) to control input of dynamic test waveforms including sinusoidal waveforms to an ADC under test (15) and to determine device under test dynamic parameters by analysing the samples. A linear test engine (5) determines device under test (15) static parameters, and controls input of ramp input waveforms to the ADC. A test controller (2) performs finite sate machine control of testing including applying test waveforms, dumping samples to the memory (7), and retrieving static and dynamic results. A DAC (3) generates controlled waveform generation under instructions from the test engines, and an interface (10) communicates with an external host. The components are linked with a bus (11) and are modular.