Patents by Inventor Brendan N. Protzman
Brendan N. Protzman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7339839Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.Type: GrantFiled: March 24, 2005Date of Patent: March 4, 2008Assignee: Micron Technology, Inc.Inventors: Brendan N Protzman, Timothy B Cowles
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Patent number: 6877064Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.Type: GrantFiled: October 31, 2002Date of Patent: April 5, 2005Assignee: Micron Technology, Inc.Inventors: Brendan N. Protzman, Timothy B. Cowles
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Patent number: 6693835Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.Type: GrantFiled: April 19, 2002Date of Patent: February 17, 2004Assignee: Micron Technology, Inc.Inventors: Brendan N. Protzman, Timothy B. Cowles
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Patent number: 6687176Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.Type: GrantFiled: October 31, 2002Date of Patent: February 3, 2004Assignee: Micron Technology, Inc.Inventors: Brendan N. Protzman, Timothy B. Cowles
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Patent number: 6574164Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.Type: GrantFiled: April 19, 2002Date of Patent: June 3, 2003Assignee: Micron Technology, Inc.Inventors: Brendan N. Protzman, Timothy B. Cowles
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Publication number: 20030079095Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.Type: ApplicationFiled: October 31, 2002Publication date: April 24, 2003Inventors: Brendan N. Protzman, Timothy B. Cowles
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Publication number: 20030076720Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.Type: ApplicationFiled: October 31, 2002Publication date: April 24, 2003Inventors: Brendan N. Protzman, Timothy B. Cowles
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Patent number: 6501688Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.Type: GrantFiled: May 30, 2001Date of Patent: December 31, 2002Assignee: Micron Technology, Inc.Inventors: Brendan N. Protzman, Timothy B. Cowles
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Patent number: 6493286Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.Type: GrantFiled: April 19, 2002Date of Patent: December 10, 2002Assignee: Micron Technology, Inc.Inventors: Brendan N. Protzman, Timothy B. Cowles
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Publication number: 20020181293Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.Type: ApplicationFiled: May 30, 2001Publication date: December 5, 2002Inventors: Brendan N. Protzman, Timothy B. Cowles
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Publication number: 20020181294Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.Type: ApplicationFiled: April 19, 2002Publication date: December 5, 2002Inventors: Brendan N. Protzman, Timothy B. Cowles
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Publication number: 20020181317Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.Type: ApplicationFiled: April 19, 2002Publication date: December 5, 2002Inventors: Brendan N. Protzman, Timothy B. Cowles
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Publication number: 20020181295Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.Type: ApplicationFiled: April 19, 2002Publication date: December 5, 2002Inventors: Brendan N. Protzman, Timothy B. Cowles
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Publication number: 20020181305Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.Type: ApplicationFiled: April 19, 2002Publication date: December 5, 2002Inventors: Brendan N. Protzman, Timothy B. Cowles
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Patent number: 6483762Abstract: A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.Type: GrantFiled: April 19, 2002Date of Patent: November 19, 2002Assignee: Micron Technology, Inc.Inventors: Brendan N. Protzman, Timothy B. Cowles
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Patent number: 6330196Abstract: An output driver includes multiple boot circuits to drive a pull-up signal of a data driver. A control circuit selects a fully precharged boot circuit when the data output by the output driver is a high signal. The remaining boot circuits not selected are allowed to fully precharge during this time in preparation for a subsequent data high signal. Consequently, any precharge delay time can be masked by selecting a fully precharged boot circuit when driving a subsequent pull-up signal.Type: GrantFiled: March 2, 2000Date of Patent: December 11, 2001Assignee: Micron Technology, Inc.Inventor: Brendan N. Protzman
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Patent number: 6141266Abstract: A delay circuit that generates an output signal responsive to an input signal after a delay corresponding to a reference voltage that is insensitive to the power supply voltage. The output signal switches between ground and the power supply voltage (V.sub.CC). The delay circuit is formed by a timer circuit and a level translator circuit. The delay circuit provides an output signal having a delay of a fixed time period regardless of fluctuations or changes in the supply voltage. The level translator circuit provides an output signal with the aforementioned delay that has a magnitude of either the power supply voltage or ground. The timer circuit includes a capacitor that is charged and discharged through respective transistors to provide the delay. The level translator circuit includes transistors that switch the output signal between the supply voltage and ground.Type: GrantFiled: August 11, 1999Date of Patent: October 31, 2000Assignee: Micron Technology, Inc.Inventors: Richard A. Mecier, Brendan N. Protzman
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Patent number: 6141263Abstract: An output driver includes multiple boot circuits to drive a pull-up signal of a data driver. A control circuit selects a fully precharged boot circuit when the data output by the output driver is a high signal. The remaining boot circuits not selected are allowed to fully precharge during this time in preparation for a subsequent data high signal. Consequently, any precharge delay time can be masked by selecting a fully precharged boot circuit when driving a subsequent pull-up signal.Type: GrantFiled: March 1, 1999Date of Patent: October 31, 2000Assignee: Micron Technology, Inc.Inventor: Brendan N. Protzman
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Patent number: 6023429Abstract: A delay circuit that generates an output signal responsive to an input signal after a delay corresponding to a reference voltage that is insensitive to the power supply voltage. The output signal switches between ground and the power supply voltage (V.sub.CC). The delay circuit is formed by a timer circuit and a level translator circuit. The delay circuit provides an output signal having a delay of a fixed time period regardless of fluctuations or changes in the supply voltage. The level translator circuit provides an output signal with the aforementioned delay that has a magnitude of either the power supply voltage or ground. The timer circuit includes a capacitor that is charged and discharged through respective transistors to provide the delay. The level translator circuit includes transistors that switch the output signal between the supply voltage and ground.Type: GrantFiled: June 5, 1998Date of Patent: February 8, 2000Assignee: Micron Technology, Inc.Inventors: Richard A. Mecier, Brendan N. Protzman