Abstract: An integrated circuit (1) comprises a microprocessor (2), an ADC (3) and a serial interface (4) for communicating the integrated circuit with an external device. An analogue input port (5) is provided for inputting analogue signals to the ADC (3). A switch circuit (8) is provided for selectively and alternately configuring the integrated circuit (1) to operate in a first mode and in a second mode. In the first mode the serial interface (4) communicates with the microprocessor (2) through the switch circuit (8), and in the second mode the serial interface (4) communicates with the ADC (3) through the switch circuit (8). In the second mode conversion results are transferred from the ADC (3) through the switch circuit (8) to the serial interface (4) independently of the microprocessor (2) for transmission therefrom to an external device. In the first mode the ADC (3) is operable under the control of the microprocessor (2).

Abstract: A concurrent processing system utilizes a generalized linearly expandable data transfer bus architecture to tightly couple data processors, memory and I/O devices. The system is suitable for multiple instruction multiple data processing, and operates by transmitting and receiving complete transaction codes fully identifying the target device by specifying a process code. Data processing memories and I/O devices may be dynamically assigned to a process by specifying the process code thus providing great flexibility in utilization of system resources. Processors, memories and I/O devices are connected together by means of interfaces which are connected to a bidirectional bus. The complete data transaction preferably occurs during one clock period, although four additional clock periods are used to complete a bus transaction, namely, arbitration, match recognition, data validation and acknowledgement of receipt.