Abstract: A method and system for performing an auction by determining a request for an item based on at least one of (i) an item to purchase, (ii) a performance specification of the item to purchase, and (iii) a term of a request for the item to purchase. The method and system include sending, through a network, the request for the item to an auctioneer machine server. Performance information is collected for each seller. Notice is provided that a performance evaluation has been received for a specific seller, and is on record with the provider of the information. Additional transaction costs may be captured and included as a separate line item in an auto-rebid auction environment.

Abstract: The present invention is directed to application of novel process conditions for aqueous coating techniques of water soluble active agents, and its application to production of sustained release beadlets of said agents. The improvement lies in the determination and use of the glass transition point for the water swellable polymer used to produce the sustained release effect, and control of the moisture content of the air by dew point.

Abstract: A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.

Abstract: An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.

Abstract: A space-conscious, functional design for a loft bed. The design serves to optimize space by incorporating multi-functional features, such as drawers, closet space, or cabinet space, within the assembly for the bed itself. Specifically, a plurality of steps are substantially parallel to the length of the bed, and lead upwardly toward the foot of the bed for easy access to same. Such steps incorporate the aforementioned storage space, with access to the drawers or closets from a side position. As such, the unique assembly allows for a desk, computer work station, bar, or additional wide storage space below the bed and behind the steps, adding to the overall versatility of the assembly. Finally, in the preferred mode the unit is modular in nature and may be assembled and rearranged based upon user preference.

Abstract: A space-conscious, functional design for a loft bed. The design serves to optimize space by incorporating multi-functional features, such as drawers, closet space, or cabinet space, within the assembly for the bed itself. Specifically, a plurality of steps are substantially parallel to the length of the bed, and lead upwardly toward the foot of the bed for easy access to same. Such steps incorporate the aforementioned storage space, with access to the drawers or closets from a side position. As such, the unique assembly allows for a desk, computer work station, bar, or additional wide storage space below the bed and behind the steps, adding to the overall versatility of the assembly. Finally, in the preferred mode the unit is modular in nature and may be assembled and rearranged based upon user preference.

Abstract: A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.

Abstract: An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths

Abstract: A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The arithmetic logic unit (230) first forms a Boolean combination and then forms an arithmetic combination. The current instruction drives an instruction decoder (250, 245) that generates the functions signals F0-F7 which control the combination formed. The three input arithmetic logic unit (230) preferably employs a set of bit circuits (400), each forming carry propagate, generate and kill signals. These signals may employed with a multilevel logic tree circuit and a carry input to produce a bit resultant and a carry output to the next bit circuit. This structure permits formation of selected arithmetic, Boolean or mixed arithmetic and Boolean function of the three input signals based upon the current instruction. Selection of the function signals enables the combination to be insensitive to one of the input signals, thus performs a two input function of remaining input signals.

Abstract: A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The current instruction drives an instruction decoder (250, 245) that generates functions signals F0-F7 which control the combination formed. The three input arithmetic logic unit (230) preferably employs a set of bit circuits (400), each forming carry propagate, generate and kill signals. These signals and a carry input produce a bit resultant and a carry output to the next bit circuit. Selection of the function signals enables the combination to be insensitive to one of the input signals, thus performing a two input function of remaining input signals. The instruction itself may include the function signals and function modification bits, or the function signals and function modification signals may be stored in a special data register. Function modification signals cause modification of the function signals prior to use.

Abstract: A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The arithmetic logic unit (230) first forms a Boolean combination and then forms an arithmetic combination. The current instruction drives an instruction decoder (250, 245) that generates the functions signals F0-F7 which control the combination formed. The three input arithmetic logic unit (230) preferably employs a set of bit circuits (400), each forming carry propagate, generate and kill signals. These signals may employed with a multilevel logic tree circuit and a carry input to produce a bit resultant and a carry output to the next bit circuit. This structure permits formation of selected arithmetic, Boolean or mixed arithmetic and Boolean function of the three input signals based upon the current instruction. Selection of the function signals enables the combination to be insensitive to one of the input signals, thus performs a two input function of remaining input signals.

Abstract: A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The arithmetic logic unit (230) first forms a Boolean combination and then forms an arithmetic combination. The current instruction drives an instruction decoder (250, 245) that generates the functions signals F0-F7 which control the combination formed. The arithmetic logic unit (230) includes a first three input Boolean function generator (496) forming a Boolean combination F1(A,B,C), a second three input Boolean function generator (497) forming a Boolean combination F2(A,B,C), and an adder (495) forming the sum of the two Boolean combinations. The first Boolean combination F1(A,B,C) and the second Boolean combination F2(A,B,C) are independently selected from the set of all possible Boolean combinations of three multibit input signals A, B and C. The adder (495) includes a least significant bit carry-in generator (246) supplying a carry input to the least significant bit.

Abstract: A programmable electronic time delay initiator includes a digital time-delay circuit that counts in response to a dual-resonator clock and, at the end of the programmed time delay, gates the pre-stored charge on a capacitor to a semiconductor bridge initiator to fire an explosive. The timer circuit includes a combined crystal/RC oscillator that provides high accuracy oscillations from the crystal or oscillations from the RC components in the event the crystal fails. The timer circuit functions in response to multi-part serial commands delivered on a conventional two-wire path. The timer is initially powered-on to provide power to a capacitor that supplies power to the time-delay and related circuits. An initial ATTENTION pulse initializes the circuitry and starts a watchdog timer that counts a fixed number of clock cycles and resets the logic if a following WRITE, ARM, or FIRE command is not received.

Abstract: Apparatus for detecting the leftmost "1" bit or the rightmost "1" bit of an input number includes a binary tree (11) of two-inputs OR-gates (13, 14, 15, 16) or their logical equivalent to which the input number is applied in parallel and from which signals are derived and applied as inputs and to control a plurality of trees (MA, MB, MC) of two-input multiplexers (12) from the outputs (E0, E1, E2, E3) of which appear the bits of a number representing the position in the input number of the leftmost "1" or the rightmost "1" bit.