Abstract: An apparatus and method for implementing a Level 0 cache within a cache subsystem. For example, one embodiment of a processor comprises: a cache subsystem comprising a Level-0 cache; a scheduler to schedule a load operation indicating data to be loaded; and a load hit predictor to predict whether the data indicated by the load operation is stored in the LO cache and to generate a wakeup signal to the scheduler in response to predicting that the data is stored in the LO cache. Some implementations perform store forwarding in response to load operations using a multi-step approach in which a partial linear address check is performed to determine load operations which are eligible for store forwarding. A full address check is performed for those load operations which are eligible in which the address of the load is compared against the address of a youngest older store operation.

Abstract: Techniques for scheduling merged store operations are described. In an embodiment, an apparatus includes a data cache; a fill buffer; a store buffer to store first information associated with a first retired store operation and second information associated with a second retired store operation; a store coalescing buffer (SCB) to receive the first information from the store buffer, to store the first information in an SCB entry, to merge the second information from the store buffer into the entry, and to provide data associated with the entry for a write to the data cache or the fill buffer; and a global store scheduler (GSS) to schedule the write relative to an other write from an other SCB in compliance with one or more store ordering rules.