Abstract: A wafer structure includes a diffractive lens disposed on a backside of a wafer and coupled to a front side waveguide, the diffractive lens being configured to receive light and focus the light to the front side waveguide.

Abstract: A wafer structure includes a diffractive lens disposed on a backside of a wafer and coupled to a front side waveguide, the diffractive lens being configured to receive light and focus the light to the front side waveguide.

Abstract: A wafer structure includes a diffractive lens disposed on a backside of a wafer and coupled to a front side waveguide, the diffractive lens being configured to receive light and focus the light to the front side waveguide.

Abstract: Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate.

Abstract: A wafer structure includes a diffractive lens disposed on a backside of a wafer and coupled to a front side waveguide, the diffractive lens being configured to receive light and focus the light to the front side waveguide.

Abstract: A wafer structure includes a diffractive lens disposed on a backside of a wafer and coupled to a front side waveguide, the diffractive lens being configured to receive light and focus the light to the front side waveguide.

Abstract: A method of manufacturing a device includes forming an optical coupler having a first end contacting a front side of a semiconductor substrate and a second end contacting an optical waveguide on an insulator layer on the substrate. The optical coupler is curved between the first end and the second end. The optical coupler is configured to change a direction of travel of light from a first direction at the first end to a second direction at the second end.

Abstract: A wafer structure includes a diffractive lens disposed on a backside of a wafer and coupled to a front side waveguide, the diffractive lens being configured to receive light and focus the light to the front side waveguide.

Abstract: A wafer structure includes a diffractive lens disposed on a backside of a wafer and coupled to a front side waveguide, the diffractive lens being configured to receive light and focus the light to the front side waveguide.

Abstract: A method of manufacturing a device includes forming an optical coupler having a first end contacting a front side of a semiconductor substrate and a second end contacting an optical waveguide on an insulator layer on the substrate. The optical coupler is curved between the first end and the second end. The optical coupler is configured to change a direction of travel of light from a first direction at the first end to a second direction at the second end.

Abstract: A wafer structure includes a diffractive lens disposed on a backside of a wafer and coupled to a front side waveguide, the diffractive lens being configured to receive light and focus the light to the front side waveguide.

Abstract: Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate.

Abstract: Si waveguide devices on a bulk Si substrate with supporting anchors and methods of manufacture are disclosed. The method includes forming a waveguide device over an Si substrate, and forming one or more anchors from the Si substrate. The one or more anchors support the waveguide device.

Abstract: Si waveguide devices on a bulk Si substrate with supporting anchors and methods of manufacture are disclosed. The method includes forming a waveguide device over an Si substrate, and forming one or more anchors from the Si substrate. The one or more anchors support the waveguide device.

Abstract: Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.

Abstract: Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.

Abstract: Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.

Abstract: Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.