Patents by Inventor Brennen K. MUELLER
Brennen K. MUELLER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230197732Abstract: In one embodiment, an integrated circuit includes a silicon substrate, a gallium nitride (GaN) layer above the silicon substrate, a bonding layer above the GaN layer, and a silicon layer above the bonding layer. Further, the integrated circuit includes a first transistor on the GaN layer and a second transistor on the silicon layer.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Paul Fischer, Kimin Jun, Brennen K. Mueller
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Patent number: 11594524Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.Type: GrantFiled: January 10, 2022Date of Patent: February 28, 2023Assignee: Intel CorporationInventors: Brennen K. Mueller, Patrick Morrow, Kimin Jun, Paul B. Fischer, Daniel Pantuso
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Publication number: 20220130803Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.Type: ApplicationFiled: January 10, 2022Publication date: April 28, 2022Inventors: Brennen K. MUELLER, Patrick MORROW, Kimin JUN, Paul B. FISCHER, Daniel PANTUSO
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Patent number: 11251156Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.Type: GrantFiled: December 23, 2015Date of Patent: February 15, 2022Assignee: Intel CorporationInventors: Brennen K. Mueller, Patrick Morrow, Kimin Jun, Paul B. Fischer, Daniel Pantuso
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Patent number: 11189585Abstract: An Integrated Circuit (IC) device comprising a first component, the first component comprising a first dielectric and a plurality of adjacent first interconnect structures within the first dielectric. The IC device comprising a second component, the second component comprising a second dielectric and a plurality of adjacent second interconnect structures within the second dielectric. A first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second components. A second of the first interconnect structures is set back a distance from a plane of the bond interface.Type: GrantFiled: December 4, 2019Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Brennen K. Mueller, Adel Elsherbini, Mauro Kobrinsky, Johanna Swan, Shawna Liff, Pooya Tadayon
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Patent number: 11056356Abstract: Techniques and mechanisms for bonding a first wafer to a second wafer in the presence of a fluid, the viscosity of which is greater than a viscosity of air at standard ambient temperature and pressure. In an embodiment, a first surface of the first wafer is brought into close proximity to a second surface of the second wafer. The fluid is provided between the first surface and the second surface when a first region of the first surface is made to contact a second region of the second surface to form a bond. The viscosity of the fluid mitigates a rate of propagation of the bond along a wafer surface, which in turn mitigates wafer deformation and/or stress between wafers. In another embodiment, the viscosity of the fluid is changed dynamically while the bond propagates between the first surface and the second surface.Type: GrantFiled: August 24, 2018Date of Patent: July 6, 2021Assignee: Intel CorporationInventors: Brennen K. Mueller, Daniel Pantuso, Mauro J. Kobrinsky, Chytra Pawashe, Myra McDonnell
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Publication number: 20210175192Abstract: An Integrated Circuit (IC) device comprising a first component, the first component comprising a first dielectric and a plurality of adjacent first interconnect structures within the first dielectric. The IC device comprising a second component, the second component comprising a second dielectric and a plurality of adjacent second interconnect structures within the second dielectric. A first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second components. A second of the first interconnect structures is set back a distance from a plane of the bond interface.Type: ApplicationFiled: December 4, 2019Publication date: June 10, 2021Applicant: Intel CorporationInventors: Brennen K. Mueller, Adel Elsherbini, Mauro Kobrinsky, Johanna Swan, Shawna Liff, Pooya Tadayon
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Patent number: 10720345Abstract: Techniques and mechanisms for forming a bond between two wafers. In an embodiment, a first wafer and a second wafer are positioned with respective wafer holders, and are deformed to form a first deformation of the first wafer and a second deformation of the second wafer. The first deformation and the second deformation are symmetrical with respect to a centerline which is between the first wafer and the second wafer. A portion of the first deformation is made to contact, and form a bond with, another portion of the second deformation. The bond is propagated along respective surfaces of the wafers to form a coupling therebetween. In another embodiment, one of the wafer holders comprises one of an array of elements to locally heat or cool a wafer, or an array of displacement stages to locally deform said wafer.Type: GrantFiled: September 7, 2018Date of Patent: July 21, 2020Assignee: Intel CorporationInventors: Mauro J. Kobrinsky, Myra McDonnell, Brennen K. Mueller, Chytra Pawashe, Daniel Pantuso, Paul B. Fischer, Lance C. Hibbeler, Martin Weiss
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Publication number: 20190057950Abstract: An embodiment includes an apparatus comprising: a first device layer included in a top edge of a semiconductor substrate; metal layers, on the first device layer, including first and second metal layers; a second device layer on the metal layers; and additional metal layers on the second device layer; wherein the second device layer is not included in any semiconductor substrate. Other embodiments are described herein.Type: ApplicationFiled: March 31, 2016Publication date: February 21, 2019Inventors: Brennen K. Mueller, Patrick Morrow, Paul B. Fischer, Kimin Jun
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Publication number: 20180323174Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.Type: ApplicationFiled: December 23, 2015Publication date: November 8, 2018Inventors: Brennen K. MUELLER, Patrick MORROW, Kimin JUN, Paul B. FISCHER, Daniel PANTUSO