Patents by Inventor Breno Henrique Leitão
Breno Henrique Leitão has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10824453Abstract: Systems and methods improve performance and resource-efficiency of Just-in-Time (JIT) compilation in a hypervisor-based virtualized computing environment. A user attempts to launch an application that has been previously compiled by a JIT compiler into an intermediate, platform-independent format. A JIT accelerator selects a unique function signature that identifies the application and the user's target platform. If the signature cannot be found in a repository, indicating that the application has never been run on the target platform, the accelerator generates and stores the requested executable program in shared memory and saves the signature in the repository. The system then returns to the user a pointer to the stored platform-specific executable. If multiple users of the same platform request the same application, the system recognizes an affinity among those requests identified by their shared signature, and provides each user a pointer to the same previously stored, shared executable.Type: GrantFiled: July 31, 2018Date of Patent: November 3, 2020Assignee: International Business Machines CorporationInventors: Rafael Camarda Silva Folco, Plinio A. S. Freire, Breno Henrique Leitao
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Publication number: 20190251255Abstract: A method, computer program product, and system for managing container security, the method including consuming a recipe queue on a first checker container, wherein the first checker container is on a first host of a computer system, and the recipe queue comprises a predefined set of rules, storing the first checker container recipe queue result in the first checker container, comparing the first checker container recipe queue result with an expected result of the recipe queue, wherein the expected result is stored in the first checker container, and following a first fail procedure from a plurality of fail procedures, based on the first checker container recipe queue result not matching the expected result.Type: ApplicationFiled: April 24, 2019Publication date: August 15, 2019Inventors: Rafael Camarda Silva Folco, Breno Henrique Leitão, Rafael Peria de Sene
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Patent number: 10331883Abstract: A method, computer program product, and system for managing container security, the method including consuming a recipe queue on a first checker container, wherein the first checker container is on a first host of a computer system, and the recipe queue comprises a predefined set of rules, storing the first checker container recipe queue result in the first checker container, comparing the first checker container recipe queue result with an expected result of the recipe queue, wherein the expected result is stored in the first checker container, and following a first fail procedure from a plurality of fail procedures, based on the first checker container recipe queue result not matching the expected result.Type: GrantFiled: September 28, 2016Date of Patent: June 25, 2019Assignee: International Business Machines CorporationInventors: Rafael Camarda Silva Folco, Breno Henrique Leitão, Rafael Peria de Sene
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Publication number: 20190087209Abstract: Systems and methods improve performance and resource-efficiency of Just-in-Time (JIT) compilation in a hypervisor-based virtualized computing environment. A user attempts to launch an application that has been previously compiled by a JIT compiler into an intermediate, platform-independent format. A JIT accelerator selects a unique function signature that identifies the application and the user's target platform. If the signature cannot be found in a repository, indicating that the application has never been run on the target platform, the accelerator generates and stores the requested executable program in shared memory and saves the signature in the repository. The system then returns to the user a pointer to the stored platform-specific executable. If multiple users of the same platform request the same application, the system recognizes an affinity among those requests identified by their shared signature, and provides each user a pointer to the same previously stored, shared executable.Type: ApplicationFiled: July 31, 2018Publication date: March 21, 2019Inventors: Rafael Camarda Silva Folco, Plinio A. S. Freire, Breno Henrique Leitao
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Patent number: 10116742Abstract: There is provided a method for managing heterogeneous cloud data storage systems across heterogeneous cloud computing systems. The method comprises: defining rules that govern storing of data in one or more of a plurality of heterogeneous cloud data storage systems; receiving complete data from a user's computer; splitting the complete data; and storing the split data according to the defined rules into the plurality of heterogeneous cloud data storage systems.Type: GrantFiled: September 15, 2014Date of Patent: October 30, 2018Assignee: International Business Machines CorporationInventors: Rafael Peria de Sene, Tiago Nune dos Santos, Rafael Camarda Silva Folco, Breno Henrique Leitao
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Patent number: 10108442Abstract: Systems and methods improve performance and resource-efficiency of Just-in-Time (JIT) compilation in a hypervisor-based virtualized computing environment. A user attempts to launch an application that has been previously compiled by a JIT compiler into an intermediate, platform-independent format. A JIT accelerator selects a unique function signature that identifies the application and the user's target platform. If the signature cannot be found in a repository, indicating that the application has never been run on the target platform, the accelerator generates and stores the requested executable program in shared memory and saves the signature in the repository. The system then returns to the user a pointer to the stored platform-specific executable. If multiple users of the same platform request the same application, the system recognizes an affinity among those requests identified by their shared signature, and provides each user a pointer to the same previously stored, shared executable.Type: GrantFiled: September 18, 2017Date of Patent: October 23, 2018Assignee: International Business Machines CorporationInventors: Rafael Camarda Silva Folco, Plinio A. S. Freire, Breno Henrique Leitao
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Patent number: 10003542Abstract: A dual chipset architecture, a method of operating a scheduler for a dual chipset architecture, and a computer program product for operating a scheduler for a dual chipset architecture. In an embodiment, the dual chipset architecture comprises a high performance processor, a low performance processor, and a scheduler for the processors. The scheduler is provided for determining an expected data traffic flow to the chipset, and for selectively enabling the high and low performance processors, based on this expected data flow, ahead of this expected data flow reaching the chipset. In one embodiment, a specified data traffic indicator is associated with the expected data traffic flow, and the scheduler uses this specified data traffic indicator to determine the expected data traffic flow. In an embodiment, this specified data traffic indicator is a value for a defined window size for the expected data flow.Type: GrantFiled: February 15, 2017Date of Patent: June 19, 2018Assignee: International Business Machines CorporationInventors: Murilo Opsfelder Araújo, Rafael Camarda Silva Folco, Breno Henrique Leitão, Tiago Nunes Dos Santos
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Patent number: 9948564Abstract: A dual chipset architecture, a method of operating a scheduler for a dual chipset architecture, and a computer program product for operating a scheduler for a dual chipset architecture. In an embodiment, the dual chipset architecture comprises a high performance processor, a low performance processor, and a scheduler for the processors. The scheduler is provided for determining an expected data traffic flow to the chipset, and for selectively enabling the high and low performance processors, based on this expected data flow, ahead of this expected data flow reaching the chipset. In one embodiment, a specified data traffic indicator is associated with the expected data traffic flow, and the scheduler uses this specified data traffic indicator to determine the expected data traffic flow. In an embodiment, this specified data traffic indicator is a value for a defined window size for the expected data flow.Type: GrantFiled: July 21, 2016Date of Patent: April 17, 2018Assignee: International Business Machines CorporationInventors: Murilo Opsfelder Araújo, Rafael Camarda Silva Folco, Breno Henrique Leitão, Tiago Nunes Dos Santos
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Publication number: 20180096141Abstract: A method, computer program product, and system for managing container security, the method including consuming a recipe queue on a first checker container, wherein the first checker container is on a first host of a computer system, and the recipe queue comprises a predefined set of rules, storing the first checker container recipe queue result in the first checker container, comparing the first checker container recipe queue result with an expected result of the recipe queue, wherein the expected result is stored in the first checker container, and following a first fail procedure from a plurality of fail procedures, based on the first checker container recipe queue result not matching the expected result.Type: ApplicationFiled: December 15, 2017Publication date: April 5, 2018Inventors: Rafael Camarda Silva Folco, Breno Henrique Leitão, Rafael Peria de Sene
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Publication number: 20180089423Abstract: A method, computer program product, and system for managing container security, the method including consuming a recipe queue on a first checker container, wherein the first checker container is on a first host of a computer system, and the recipe queue comprises a predefined set of rules, storing the first checker container recipe queue result in the first checker container, comparing the first checker container recipe queue result with an expected result of the recipe queue, wherein the expected result is stored in the first checker container, and following a first fail procedure from a plurality of fail procedures, based on the first checker container recipe queue result not matching the expected result.Type: ApplicationFiled: September 28, 2016Publication date: March 29, 2018Inventors: Rafael Camarda Silva Folco, Breno Henrique Leitão, Rafael Peria de Sene
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Patent number: 9858239Abstract: There is provided a method for operating of network cards in computing systems. The method comprises: detecting resource utilization of all network cards of computing systems connected via the one or more networks; monitoring network statistics of the network, the monitoring the network statistics including: evaluating whether a resource utilization of each network card connected to the one more networks is larger than a threshold; and determining an operation of each network card connected to the network according to and the detected resource utilization and the monitored network statistics.Type: GrantFiled: September 15, 2014Date of Patent: January 2, 2018Assignee: International Business Machines CorporationInventors: Kleber Sacilotto de Souza, Tiago Nunes dos Santos, Rafael Camarda Silva Folco, Breno Henrique Leitão
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Publication number: 20170163546Abstract: A dual chipset architecture, a method of operating a scheduler for a dual chipset architecture, and a computer program product for operating a scheduler for a dual chipset architecture. In an embodiment, the dual chipset architecture comprises a high performance processor, a low performance processor, and a scheduler for the processors. The scheduler is provided for determining an expected data traffic flow to the chipset, and for selectively enabling the high and low performance processors, based on this expected data flow, ahead of this expected data flow reaching the chipset. In one embodiment, a specified data traffic indicator is associated with the expected data traffic flow, and the scheduler uses this specified data traffic indicator to determine the expected data traffic flow. In an embodiment, this specified data traffic indicator is a value for a defined window size for the expected data flow.Type: ApplicationFiled: February 15, 2017Publication date: June 8, 2017Inventors: Murilo Opsfelder Araújo, Rafael Camarda Silva Folco, Breno Henrique Leitão, Tiago Nunes Dos Santos
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Patent number: 9652432Abstract: There are provided a system and a computer program product for operating of network cards in computing systems. The computing systems detect resource utilization of all network cards of physical servers connected via one or more networks. The computing systems monitor network statistics of the network. The computing systems determine an operation of each network card connected to the network according to the monitored network statistics.Type: GrantFiled: April 8, 2014Date of Patent: May 16, 2017Assignee: International Business Machines CorporationInventors: Kleber Sacilotto de Souza, Tiago Nunes dos Santos, Rafael Camarda Silva Folco, Breno Henrique Leitão
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Patent number: 9577945Abstract: A dual chipset architecture, a method of operating a scheduler for a dual chipset architecture, and a computer program product for operating a scheduler for a dual chipset architecture. In an embodiment, the dual chipset architecture comprises a high performance processor, a low performance processor, and a scheduler for the processors. The scheduler is provided for determining an expected data traffic flow to the chipset, and for selectively enabling the high and low performance processors, based on this expected data flow, ahead of this expected data flow reaching the chipset. In one embodiment, a specified data traffic indicator is associated with the expected data traffic flow, and the scheduler uses this specified data traffic indicator to determine the expected data traffic flow. In an embodiment, this specified data traffic indicator is a value for a defined window size for the expected data flow.Type: GrantFiled: September 12, 2014Date of Patent: February 21, 2017Assignee: International Business Machines CorporationInventors: Murilo Opsfelder Araújo, Rafael Camarda Silva Folco, Breno Henrique Leitão, Tiago Nunes dos Santos
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Patent number: 9565253Abstract: There are provided a system and a computer program product for managing heterogeneous cloud data storage systems. A computing system defines rules that govern a plurality of heterogeneous cloud data storage systems. The computing system receives complete data from a user's computer. The computing system splits the complete data. The computing system stores the split data according to the defined rules into the plurality of heterogeneous cloud data storage systems.Type: GrantFiled: July 21, 2014Date of Patent: February 7, 2017Assignee: International Business Machines CorporationInventors: Rafael Peria de Sene, Tiago Nunes dos Santos, Rafael Camarda Silva Folco, Breno Henrique Leitao
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Publication number: 20160330126Abstract: A dual chipset architecture, a method of operating a scheduler for a dual chipset architecture, and a computer program product for operating a scheduler for a dual chipset architecture. In an embodiment, the dual chipset architecture comprises a high performance processor, a low performance processor, and a scheduler for the processors. The scheduler is provided for determining an expected data traffic flow to the chipset, and for selectively enabling the high and low performance processors, based on this expected data flow, ahead of this expected data flow reaching the chipset. In one embodiment, a specified data traffic indicator is associated with the expected data traffic flow, and the scheduler uses this specified data traffic indicator to determine the expected data traffic flow. In an embodiment, this specified data traffic indicator is a value for a defined window size for the expected data flow.Type: ApplicationFiled: July 21, 2016Publication date: November 10, 2016Inventors: Murilo Opsfelder Araújo, Rafael Camarda Silva Folco, Breno Henrique Leitão, Tiago Nunes Dos Santos
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Patent number: 9419905Abstract: A dual chipset architecture, a method of operating a scheduler for a dual chipset architecture, and a computer program product for operating a scheduler for a dual chipset architecture. In an embodiment, the dual chipset architecture comprises a high performance processor, a low performance processor, and a scheduler for the processors. The scheduler is provided for determining an expected data traffic flow to the chipset, and for selectively enabling the high and low performance processors, based on this expected data flow, ahead of this expected data flow reaching the chipset. In one embodiment, a specified data traffic indicator is associated with the expected data traffic flow, and the scheduler uses this specified data traffic indicator to determine the expected data traffic flow. In an embodiment, this specified data traffic indicator is a value for a defined window size for the expected data flow.Type: GrantFiled: April 4, 2014Date of Patent: August 16, 2016Assignee: International Business Machines CorporationInventors: Murilo Opsfelder Araújo, Rafael Camarda Silva Folco, Breno Henrique Leitão, Tiago Nunes dos Santos
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Publication number: 20160021185Abstract: There are provided a system and a computer program product for managing heterogeneous cloud data storage systems. A computing system defines rules that govern a plurality of heterogeneous cloud data storage systems. The computing system receives complete data from a user's computer. The computing system splits the complete data. The computing system stores the split data according to the defined rules into the plurality of heterogeneous cloud data storage systems.Type: ApplicationFiled: July 21, 2014Publication date: January 21, 2016Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rafael Peria de Sene, Tiago Nunes dos Santos, Rafael Camarda Silva Folco, Breno Henrique Leitao
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Publication number: 20160021186Abstract: There is provided a method for managing heterogeneous cloud data storage systems across heterogeneous cloud computing systems. The method comprises: defining rules that govern storing of data in one or more of a plurality of heterogeneous cloud data storage systems; receiving complete data from a user's computer; splitting the complete data; and storing the split data according to the defined rules into the plurality of heterogeneous cloud data storage systems.Type: ApplicationFiled: September 15, 2014Publication date: January 21, 2016Inventors: Rafael Peria de Sene, Tiago Nune dos Santos, Rafael Camarda Silva Folco, Breno Henrique Leitao
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Patent number: 9161207Abstract: An apparatus and system for seamless transition between WiFi networks (including in particular WiFi Internet networks) includes within a mobile communication apparatus a mobility layer that is tunneled to a mobility server within a network infrastructure. The mobile communications apparatus includes a wireless network capability, a global positioning system capability, an internal network protocol address and a routing capability. The apparatus and system also provide that the mobility layer is programmed to sequentially and automatically tunnel to the mobility server at an available geographically defined WiFi network access location predicated upon a global positioning system determined position of the mobile communication apparatus. Embodiments also provide seamless transitions between WiFi networks and cellular networks.Type: GrantFiled: August 18, 2014Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Lucas Goncalves Franco, Peeyush Jaiswal, Breno Henrique Leitao, Christopher A. Robbins