Patents by Inventor Brenor Brophy
Brenor Brophy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8668960Abstract: Disclosed is a flow coating apparatus, comprising a slot that can dispense a coating material in an approximately uniform manner along a distribution blade that increases uniformity by means of surface tension and transfers the uniform flow of coating material onto an inclined substrate such as for example glass, solar panels, windows or part of an electronic display. Also disclosed is a method of flow coating a substrate using the apparatus such that the substrate is positioned correctly relative to the distribution blade, a pre-wetting step is completed where both the blade and substrate are completed wetted with a pre-wet solution prior to dispensing of the coating material onto the distribution blade from the slot and hence onto the substrate. Thereafter the substrate is removed from the distribution blade and allowed to dry, thereby forming a coating.Type: GrantFiled: March 15, 2013Date of Patent: March 11, 2014Assignee: Enki Technology, Inc.Inventors: Ramasubrahmaniam Hanumanthu, Patrick Neyman, Niles MacDonald, Brenor Brophy, Kevin Kopczynski, Vinod Nair
-
Patent number: 7129722Abstract: The quality and reliability of electro-optical modules can be improved, for instance, through improved testing and burn-in of an electro-optical sub-assembly. Reliability can also be enhanced through better methods of constructing an electro-optical module. By arranging both an electrical interface and an optical interface on a sub-assembly, for instance, testing can be performed on both interfaces in a single testing process. Burning-in an electro-optical sub-assembly can also improve the reliability of the module by identifying defects. A method of forming an electro-optical module can provide improved reliability by testing and/or burning-in an electro-optical sub-assembly before assembling the module.Type: GrantFiled: October 9, 2002Date of Patent: October 31, 2006Assignee: Cypress Semiconductor Corp.Inventors: Brenor Brophy, Marc Hartranft, Syed Tariq Shafaat, Jeff Hall
-
Patent number: 6892449Abstract: A method of manufacturing a plurality of electro-optical sub-assemblies in parallel is provided. A plurality of printed circuit boards (PCBs) are preferably formed in a panel of flex material. Rigid substrates can be arranged along regions of the PCBs. A plurality of electrical components, including electro-optical semiconductor devices, are preferably located on the rigid substrates. Lens arrays are preferably aligned over the electro-optical semiconductor devices, such as through an alignment mechanism. The PCBs can then be singulated into individual electro-optical sub-assemblies. The rigid substrates can be a plurality of leadframes formed on a matrix leadframe. The matrix leadframe is preferably attached to the panel of flex material such that the leadframes are arranged in proximity to leadframe cutout regions of the PCBs. Electrical interconnections are then preferably formed between the electrical components on the leadframe and the PCBs.Type: GrantFiled: October 9, 2002Date of Patent: May 17, 2005Assignee: Cypress Semiconductor Corp.Inventors: Brenor Brophy, Marc Hartranft, Syed Tariq Shafaat, Jeff Hall
-
Patent number: 6890107Abstract: An electro-optical apparatus constructed according to various inventive principles disclosed herein provides flexibility in the type and arrangement of components. The electro-optical apparatus preferably includes a Printed Circuit Board (PCB). An interface device can be electrically connected to the PCB, and an electro-optical device can be electrically connected to the interface device. A lens is preferably arranged in optical communication with the electro-optical device. Numerous variations in component selection and arrangement are contemplated within the scope of these inventive principles. Various methods for configuring an electro-optical apparatus are also provided.Type: GrantFiled: October 9, 2002Date of Patent: May 10, 2005Assignee: Cypress Semiconductor Corp.Inventors: Brenor Brophy, Marc Hartranft, Syed Tariq Shafaat, Jeff Hall
-
Patent number: 6815729Abstract: An electro-optical device preferably includes a printed circuit board (PCB) having a cutout region or a rigid region. A leadframe having an electro-optical semiconductor device arranged thereon can be arranged in proximity to the cutout region of the PCB. Alternatively, the electro-optical device can be arranged on the rigid region of the PCB. A lens is preferably arranged over the electro-optical semiconductor device. A connector array can also be arranged on the PCB to communicate electrical signals with an external device. An interface circuit, such as a driver circuit or an amplifier circuit, can also be arranged in close proximity to the electro-optical semiconductor devices on the leadframe or the PCB.Type: GrantFiled: October 9, 2002Date of Patent: November 9, 2004Assignee: Cypress Semiconductor Corp.Inventors: Brenor Brophy, Marc Hartranft, Syed Tariq Shafaat, Jeff Hall
-
Patent number: 6731009Abstract: A multi-chip integrated circuit assembly including embodiments having a plurality of integrated circuits connected thereto. According to one embodiment, a multi-chip assembly (100) may include a first surface (102) having first surface connections (106) and a second surface (104) having second surface connections (108). A first surface (102) may be lower than a second surface (104). First and/or second surface connections (106 and 108) may have conductive paths to one another and/or to assembly connections (110). In one particular arrangement, first and second surface connections (106 and 108) may provide “flip-chip” type connections to integrated circuits. Assembly connections (110) may provide a ball grid array (BGA) type connection for the multi-chip assembly (100).Type: GrantFiled: March 20, 2000Date of Patent: May 4, 2004Assignee: Cypress Semiconductor CorporationInventors: Christopher W. Jones, Brenor Brophy
-
Patent number: 6657241Abstract: A semiconductor device includes a grounded-gate n-channel field effect transistor (FET) between an I/O pad and ground (Vss) and/or Vcc for providing ESD protection. The FET includes a tap region of grounded p-type semiconductor material in the vicinity of the n+-type source region of the FET, which is also tied to ground, to make the ESD protection device less sensitive to substrate noise. The p-type tap region comprises either (i) a plurality of generally bar shaped subregions disposed in parallel relation to n+ source subregions, or, (ii) a region that is generally annular in shape and surrounds the n+ source region. The p-type tap region functions to inhibit or prevent snapback of the ESD device, particularly inadvertent conduction of a parasitic lateral npn bipolar transistor, resulting from substrate noise during programming operations on an EPROM device or in general used in situations where high voltages close to but lower than the snapback voltage are required in the pin.Type: GrantFiled: April 10, 1998Date of Patent: December 2, 2003Assignee: Cypress Semiconductor Corp.Inventors: Mark W. Rouse, Andrew Walker, Brenor Brophy, Kenelm Murray
-
Patent number: 6637017Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of signals in response to one or more input signals. The second circuit may be configured to generate one or more control signals in response to said plurality of signals. The one or more control signals may control one or more non-logic features.Type: GrantFiled: March 17, 2000Date of Patent: October 21, 2003Assignee: Cypress Semiconductor Corp.Inventor: Brenor Brophy